b8133c1997
* Started to rewrite the thread scheduler * Add a single core-like scheduling mode, enabled by default * Clear exclusive monitor on context switch * Add SetThreadActivity, misc fixes * Implement WaitForAddress and SignalToAddress svcs, misc fixes * Misc fixes (on SetActivity and Arbiter), other tweaks * Rebased * Add missing null check * Rename multicore key on config, fix UpdatePriorityInheritance * Make scheduling data MLQs private * nit: Ordering
192 lines
No EOL
6 KiB
C#
192 lines
No EOL
6 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Threading;
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using static ChocolArm64.Instruction.AInstEmitMemoryHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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[Flags]
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private enum AccessType
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{
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None = 0,
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Ordered = 1,
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Exclusive = 2,
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OrderedEx = Ordered | Exclusive
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}
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public static void Clrex(AILEmitterCtx Context)
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{
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EmitMemoryCall(Context, nameof(AMemory.ClearExclusive));
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}
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public static void Dmb(AILEmitterCtx Context) => EmitBarrier(Context);
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public static void Dsb(AILEmitterCtx Context) => EmitBarrier(Context);
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public static void Ldar(AILEmitterCtx Context) => EmitLdr(Context, AccessType.Ordered);
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public static void Ldaxr(AILEmitterCtx Context) => EmitLdr(Context, AccessType.OrderedEx);
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public static void Ldxr(AILEmitterCtx Context) => EmitLdr(Context, AccessType.Exclusive);
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public static void Ldxp(AILEmitterCtx Context) => EmitLdp(Context, AccessType.Exclusive);
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public static void Ldaxp(AILEmitterCtx Context) => EmitLdp(Context, AccessType.OrderedEx);
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private static void EmitLdr(AILEmitterCtx Context, AccessType AccType)
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{
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EmitLoad(Context, AccType, false);
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}
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private static void EmitLdp(AILEmitterCtx Context, AccessType AccType)
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{
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EmitLoad(Context, AccType, true);
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}
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private static void EmitLoad(AILEmitterCtx Context, AccessType AccType, bool Pair)
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{
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AOpCodeMemEx Op = (AOpCodeMemEx)Context.CurrOp;
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bool Ordered = (AccType & AccessType.Ordered) != 0;
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bool Exclusive = (AccType & AccessType.Exclusive) != 0;
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if (Ordered)
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{
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EmitBarrier(Context);
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}
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if (Exclusive)
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{
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EmitMemoryCall(Context, nameof(AMemory.SetExclusive), Op.Rn);
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}
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Context.EmitLdint(Op.Rn);
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Context.EmitSttmp();
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdtmp();
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EmitReadZxCall(Context, Op.Size);
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Context.EmitStintzr(Op.Rt);
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if (Pair)
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{
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdtmp();
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Context.EmitLdc_I8(1 << Op.Size);
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Context.Emit(OpCodes.Add);
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EmitReadZxCall(Context, Op.Size);
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Context.EmitStintzr(Op.Rt2);
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}
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}
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public static void Pfrm(AILEmitterCtx Context)
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{
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//Memory Prefetch, execute as no-op.
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}
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public static void Stlr(AILEmitterCtx Context) => EmitStr(Context, AccessType.Ordered);
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public static void Stlxr(AILEmitterCtx Context) => EmitStr(Context, AccessType.OrderedEx);
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public static void Stxr(AILEmitterCtx Context) => EmitStr(Context, AccessType.Exclusive);
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public static void Stxp(AILEmitterCtx Context) => EmitStp(Context, AccessType.Exclusive);
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public static void Stlxp(AILEmitterCtx Context) => EmitStp(Context, AccessType.OrderedEx);
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private static void EmitStr(AILEmitterCtx Context, AccessType AccType)
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{
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EmitStore(Context, AccType, false);
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}
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private static void EmitStp(AILEmitterCtx Context, AccessType AccType)
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{
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EmitStore(Context, AccType, true);
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}
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private static void EmitStore(AILEmitterCtx Context, AccessType AccType, bool Pair)
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{
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AOpCodeMemEx Op = (AOpCodeMemEx)Context.CurrOp;
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bool Ordered = (AccType & AccessType.Ordered) != 0;
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bool Exclusive = (AccType & AccessType.Exclusive) != 0;
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if (Ordered)
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{
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EmitBarrier(Context);
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}
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AILLabel LblEx = new AILLabel();
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AILLabel LblEnd = new AILLabel();
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if (Exclusive)
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{
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EmitMemoryCall(Context, nameof(AMemory.TestExclusive), Op.Rn);
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Context.Emit(OpCodes.Brtrue_S, LblEx);
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Context.EmitLdc_I8(1);
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Context.EmitStintzr(Op.Rs);
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Context.Emit(OpCodes.Br_S, LblEnd);
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}
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Context.MarkLabel(LblEx);
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdint(Op.Rn);
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Context.EmitLdintzr(Op.Rt);
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EmitWriteCall(Context, Op.Size);
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if (Pair)
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{
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdint(Op.Rn);
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Context.EmitLdc_I8(1 << Op.Size);
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Context.Emit(OpCodes.Add);
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Context.EmitLdintzr(Op.Rt2);
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EmitWriteCall(Context, Op.Size);
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}
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if (Exclusive)
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{
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Context.EmitLdc_I8(0);
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Context.EmitStintzr(Op.Rs);
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EmitMemoryCall(Context, nameof(AMemory.ClearExclusiveForStore));
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}
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Context.MarkLabel(LblEnd);
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}
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private static void EmitMemoryCall(AILEmitterCtx Context, string Name, int Rn = -1)
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{
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Core));
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if (Rn != -1)
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{
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Context.EmitLdint(Rn);
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}
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Context.EmitCall(typeof(AMemory), Name);
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}
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private static void EmitBarrier(AILEmitterCtx Context)
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{
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//Note: This barrier is most likely not necessary, and probably
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//doesn't make any difference since we need to do a ton of stuff
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//(software MMU emulation) to read or write anything anyway.
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Context.EmitCall(typeof(Thread), nameof(Thread.MemoryBarrier));
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}
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}
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} |