mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-20 07:38:42 +02:00
* Turn `MemoryOperand` into a struct * Remove `IntrinsicOperation` * Remove `PhiNode` * Remove `Node` * Turn `Operand` into a struct * Turn `Operation` into a struct * Clean up pool management methods * Add `Arena` allocator * Move `OperationHelper` to `Operation.Factory` * Move `OperandHelper` to `Operand.Factory` * Optimize `Operation` a bit * Fix `Arena` initialization * Rename `NativeList<T>` to `ArenaList<T>` * Reduce `Operand` size from 88 to 56 bytes * Reduce `Operation` size from 56 to 40 bytes * Add optimistic interning of Register & Constant operands * Optimize `RegisterUsage` pass a bit * Optimize `RemoveUnusedNodes` pass a bit Iterating in reverse-order allows killing dependency chains in a single pass. * Fix PPTC symbols * Optimize `BasicBlock` a bit Reduce allocations from `_successor` & `DominanceFrontiers` * Fix `Operation` resize * Make `Arena` expandable Change the arena allocator to be expandable by allocating in pages, with some of them being pooled. Currently 32 pages are pooled. An LRU removal mechanism should probably be added to it. Apparently MHR can allocate bitmaps large enough to exceed the 16MB limit for the type. * Move `Arena` & `ArenaList` to `Common` * Remove `ThreadStaticPool` & co * Add `PhiOperation` * Reduce `Operand` size from 56 from 48 bytes * Add linear-probing to `Operand` intern table * Optimize `HybridAllocator` a bit * Add `Allocators` class * Tune `ArenaAllocator` sizes * Add page removal mechanism to `ArenaAllocator` Remove pages which have not been used for more than 5s after each reset. I am on fence if this would be better using a Gen2 callback object like the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right now if a large translation happens, the pages will be freed only after a reset. This reset may not happen for a while because no new translation is hit, but the arena base sizes are rather small. * Fix `OOM` when allocating larger than page size in `ArenaAllocator` Tweak resizing mechanism for Operand.Uses and Assignemnts. * Optimize `Optimizer` a bit * Optimize `Operand.Add<T>/Remove<T>` a bit * Clean up `PreAllocator` * Fix phi insertion order Reduce codegen diffs. * Fix code alignment * Use new heuristics for degree of parallelism * Suppress warnings * Address gdkchan's feedback Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that `Operand.Value` should usually not be modified directly. * Add fast path to `ArenaAllocator` * Assembly for `ArenaAllocator.Allocate(ulong)`: .L0: mov rax, [rcx+0x18] lea r8, [rax+rdx] cmp r8, [rcx+0x10] ja short .L2 .L1: mov rdx, [rcx+8] add rax, [rdx+8] mov [rcx+0x18], r8 ret .L2: jmp ArenaAllocator.AllocateSlow(UInt64) A few variable/field had to be changed to ulong so that RyuJIT avoids emitting zero-extends. * Implement a new heuristic to free pooled pages. If an arena is used often, it is more likely that its pages will be needed, so the pages are kept for longer (e.g: during PPTC rebuild or burst sof compilations). If is not used often, then it is more likely that its pages will not be needed (e.g: after PPTC rebuild or bursts of compilations). * Address riperiperi's feedback * Use `EqualityComparer<T>` in `IntrusiveList<T>` Avoids a potential GC hole in `Equals(T, T)`.
256 lines
8.9 KiB
C#
256 lines
8.9 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitHelper
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{
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public static bool IsThumb(OpCode op)
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{
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return op is OpCodeT16;
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}
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public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType type)
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{
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Operand value = GetIntOrZR(context, rm);
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switch (type)
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{
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case IntType.UInt8: value = context.ZeroExtend8 (value.Type, value); break;
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case IntType.UInt16: value = context.ZeroExtend16(value.Type, value); break;
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case IntType.UInt32: value = context.ZeroExtend32(value.Type, value); break;
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case IntType.Int8: value = context.SignExtend8 (value.Type, value); break;
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case IntType.Int16: value = context.SignExtend16(value.Type, value); break;
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case IntType.Int32: value = context.SignExtend32(value.Type, value); break;
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}
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return value;
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}
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public static Operand GetIntA32(ArmEmitterContext context, int regIndex)
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{
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if (regIndex == RegisterAlias.Aarch32Pc)
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{
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OpCode32 op = (OpCode32)context.CurrOp;
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return Const((int)op.GetPc());
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}
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else
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{
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return Register(GetRegisterAlias(context.Mode, regIndex), RegisterType.Integer, OperandType.I32);
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}
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}
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public static Operand GetVecA32(int regIndex)
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{
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return Register(regIndex, RegisterType.Vector, OperandType.V128);
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}
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public static void SetIntA32(ArmEmitterContext context, int regIndex, Operand value)
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{
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if (regIndex == RegisterAlias.Aarch32Pc)
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{
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if (!IsA32Return(context))
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{
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context.StoreToContext();
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}
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EmitBxWritePc(context, value);
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}
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else
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{
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if (value.Type == OperandType.I64)
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{
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value = context.ConvertI64ToI32(value);
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}
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Operand reg = Register(GetRegisterAlias(context.Mode, regIndex), RegisterType.Integer, OperandType.I32);
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context.Copy(reg, value);
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}
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}
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public static int GetRegisterAlias(Aarch32Mode mode, int regIndex)
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{
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// Only registers >= 8 are banked,
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// with registers in the range [8, 12] being
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// banked for the FIQ mode, and registers
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// 13 and 14 being banked for all modes.
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if ((uint)regIndex < 8)
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{
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return regIndex;
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}
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return GetBankedRegisterAlias(mode, regIndex);
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}
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public static int GetBankedRegisterAlias(Aarch32Mode mode, int regIndex)
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{
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switch (regIndex)
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{
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case 8: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R8Fiq
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: RegisterAlias.R8Usr;
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case 9: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R9Fiq
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: RegisterAlias.R9Usr;
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case 10: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R10Fiq
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: RegisterAlias.R10Usr;
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case 11: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R11Fiq
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: RegisterAlias.R11Usr;
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case 12: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R12Fiq
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: RegisterAlias.R12Usr;
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case 13:
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switch (mode)
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{
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case Aarch32Mode.User:
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case Aarch32Mode.System: return RegisterAlias.SpUsr;
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case Aarch32Mode.Fiq: return RegisterAlias.SpFiq;
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case Aarch32Mode.Irq: return RegisterAlias.SpIrq;
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case Aarch32Mode.Supervisor: return RegisterAlias.SpSvc;
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case Aarch32Mode.Abort: return RegisterAlias.SpAbt;
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case Aarch32Mode.Hypervisor: return RegisterAlias.SpHyp;
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case Aarch32Mode.Undefined: return RegisterAlias.SpUnd;
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default: throw new ArgumentException(nameof(mode));
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}
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case 14:
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switch (mode)
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{
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case Aarch32Mode.User:
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case Aarch32Mode.Hypervisor:
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case Aarch32Mode.System: return RegisterAlias.LrUsr;
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case Aarch32Mode.Fiq: return RegisterAlias.LrFiq;
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case Aarch32Mode.Irq: return RegisterAlias.LrIrq;
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case Aarch32Mode.Supervisor: return RegisterAlias.LrSvc;
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case Aarch32Mode.Abort: return RegisterAlias.LrAbt;
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case Aarch32Mode.Undefined: return RegisterAlias.LrUnd;
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default: throw new ArgumentException(nameof(mode));
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}
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default: throw new ArgumentOutOfRangeException(nameof(regIndex));
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}
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}
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public static bool IsA32Return(ArmEmitterContext context)
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{
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switch (context.CurrOp)
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{
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case IOpCode32MemMult op:
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return true; // Setting PC using LDM is nearly always a return.
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case OpCode32AluRsImm op:
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return op.Rm == RegisterAlias.Aarch32Lr;
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case OpCode32AluRsReg op:
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return op.Rm == RegisterAlias.Aarch32Lr;
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case OpCode32AluReg op:
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return op.Rm == RegisterAlias.Aarch32Lr;
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case OpCode32Mem op:
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return op.Rn == RegisterAlias.Aarch32Sp && op.WBack && !op.Index; // Setting PC to an address stored on the stack is nearly always a return.
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}
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return false;
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}
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public static void EmitBxWritePc(ArmEmitterContext context, Operand pc, int sourceRegister = 0)
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{
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bool isReturn = sourceRegister == RegisterAlias.Aarch32Lr || IsA32Return(context);
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Operand mode = context.BitwiseAnd(pc, Const(1));
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SetFlag(context, PState.TFlag, mode);
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Operand addr = context.ConditionalSelect(mode, pc, context.BitwiseAnd(pc, Const(~3)));
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InstEmitFlowHelper.EmitVirtualJump(context, addr, isReturn);
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}
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public static Operand GetIntOrZR(ArmEmitterContext context, int regIndex)
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{
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if (regIndex == RegisterConsts.ZeroIndex)
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{
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OperandType type = context.CurrOp.GetOperandType();
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return type == OperandType.I32 ? Const(0) : Const(0L);
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}
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else
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{
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return GetIntOrSP(context, regIndex);
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}
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}
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public static void SetIntOrZR(ArmEmitterContext context, int regIndex, Operand value)
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{
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if (regIndex == RegisterConsts.ZeroIndex)
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{
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return;
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}
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SetIntOrSP(context, regIndex, value);
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}
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public static Operand GetIntOrSP(ArmEmitterContext context, int regIndex)
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{
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Operand value = Register(regIndex, RegisterType.Integer, OperandType.I64);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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value = context.ConvertI64ToI32(value);
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}
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return value;
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}
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public static void SetIntOrSP(ArmEmitterContext context, int regIndex, Operand value)
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{
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Operand reg = Register(regIndex, RegisterType.Integer, OperandType.I64);
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if (value.Type == OperandType.I32)
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{
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value = context.ZeroExtend32(OperandType.I64, value);
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}
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context.Copy(reg, value);
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}
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public static Operand GetVec(int regIndex)
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{
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return Register(regIndex, RegisterType.Vector, OperandType.V128);
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}
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public static Operand GetFlag(PState stateFlag)
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{
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return Register((int)stateFlag, RegisterType.Flag, OperandType.I32);
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}
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public static Operand GetFpFlag(FPState stateFlag)
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{
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return Register((int)stateFlag, RegisterType.FpFlag, OperandType.I32);
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}
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public static void SetFlag(ArmEmitterContext context, PState stateFlag, Operand value)
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{
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context.Copy(GetFlag(stateFlag), value);
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context.MarkFlagSet(stateFlag);
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}
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public static void SetFpFlag(ArmEmitterContext context, FPState stateFlag, Operand value)
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{
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context.Copy(GetFpFlag(stateFlag), value);
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}
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}
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}
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