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https://github.com/Ryujinx/Ryujinx.git
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89ccec197e
* Implement VMOVL and VORR.I32 AArch32 SIMD instructions * Rename <dt> to <size> on test description * Rename Widen to Long and improve VMOVL implementation a bit
90 lines
2.7 KiB
C#
90 lines
2.7 KiB
C#
#define SimdLogical32
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using ARMeilleure.State;
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using NUnit.Framework;
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using System;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdLogical32")]
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public sealed class CpuTestSimdLogical32 : CpuTest32
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{
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#if SimdLogical32
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#region "ValueSource (Opcodes)"
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private static uint[] _Vbif_Vbit_Vbsl_Vand_()
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{
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return new uint[]
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{
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0xf3300110u, // VBIF D0, D0, D0
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0xf3200110u, // VBIT D0, D0, D0
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0xf3100110u, // VBSL D0, D0, D0
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0xf2000110u // VAND D0, D0, D0
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};
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}
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#endregion
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private const int RndCnt = 2;
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[Test, Pairwise]
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public void Vbif_Vbit_Vbsl_Vand([ValueSource("_Vbif_Vbit_Vbsl_Vand_")] uint opcode,
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[Range(0u, 4u)] uint rd,
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[Range(0u, 4u)] uint rn,
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[Range(0u, 4u)] uint rm,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b,
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[Values] bool q)
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{
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if (q)
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{
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opcode |= 1 << 6;
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rm <<= 1;
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rn <<= 1;
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rd <<= 1;
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}
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VORR.I32 <Vd>, #<imm>")]
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public void Vorr_II([Range(0u, 4u)] uint rd,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] byte imm,
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[Values(0u, 1u, 2u, 3u)] uint cMode,
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[Values] bool q)
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{
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uint opcode = 0xf2800110u; // VORR.I32 D0, #0
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if (q)
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{
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opcode |= 1 << 6;
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rd <<= 1;
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}
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opcode |= (uint)(imm & 0xf) << 0;
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opcode |= (uint)(imm & 0x70) << 12;
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opcode |= (uint)(imm & 0x80) << 17;
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opcode |= (cMode & 0x3) << 9;
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcode, v0: v0);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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