264 lines
7.2 KiB
C#
264 lines
7.2 KiB
C#
using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("Misc"), Explicit]
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public sealed class CpuTestMisc : CpuTest
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{
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[TestCase(0xFFFFFFFDu)] // Roots.
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[TestCase(0x00000005u)]
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public void Misc1(uint A)
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{
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// ((A + 3) * (A - 5)) / ((A + 5) * (A - 3)) = 0
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/*
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ADD W2, W0, 3
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SUB W1, W0, #5
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MUL W2, W2, W1
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ADD W1, W0, 5
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SUB W0, W0, #3
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MUL W0, W1, W0
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SDIV W0, W2, W0
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BRK #0
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RET
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*/
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SetThreadState(X0: A);
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Opcode(0x11000C02);
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Opcode(0x51001401);
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Opcode(0x1B017C42);
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Opcode(0x11001401);
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Opcode(0x51000C00);
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Opcode(0x1B007C20);
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Opcode(0x1AC00C40);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetThreadState().X0, Is.Zero);
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}
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[TestCase(-20f, -5f)] // 18 integer solutions.
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[TestCase(-12f, -6f)]
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[TestCase(-12f, 3f)]
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[TestCase( -8f, -8f)]
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[TestCase( -6f, -12f)]
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[TestCase( -5f, -20f)]
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[TestCase( -4f, 2f)]
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[TestCase( -3f, 12f)]
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[TestCase( -2f, 4f)]
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[TestCase( 2f, -4f)]
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[TestCase( 3f, -12f)]
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[TestCase( 4f, -2f)]
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[TestCase( 5f, 20f)]
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[TestCase( 6f, 12f)]
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[TestCase( 8f, 8f)]
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[TestCase( 12f, -3f)]
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[TestCase( 12f, 6f)]
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[TestCase( 20f, 5f)]
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public void Misc2(float A, float B)
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{
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// 1 / ((1 / A + 1 / B) ^ 2) = 16
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/*
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FMOV S2, 1.0e+0
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FDIV S0, S2, S0
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FDIV S1, S2, S1
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FADD S0, S0, S1
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FDIV S0, S2, S0
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FMUL S0, S0, S0
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BRK #0
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RET
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*/
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SetThreadState(V0: new AVec { S0 = A }, V1: new AVec { S0 = B });
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Opcode(0x1E2E1002);
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Opcode(0x1E201840);
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Opcode(0x1E211841);
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Opcode(0x1E212800);
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Opcode(0x1E201840);
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Opcode(0x1E200800);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetThreadState().V0.S0, Is.EqualTo(16f));
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}
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[TestCase(-20d, -5d)] // 18 integer solutions.
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[TestCase(-12d, -6d)]
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[TestCase(-12d, 3d)]
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[TestCase( -8d, -8d)]
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[TestCase( -6d, -12d)]
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[TestCase( -5d, -20d)]
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[TestCase( -4d, 2d)]
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[TestCase( -3d, 12d)]
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[TestCase( -2d, 4d)]
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[TestCase( 2d, -4d)]
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[TestCase( 3d, -12d)]
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[TestCase( 4d, -2d)]
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[TestCase( 5d, 20d)]
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[TestCase( 6d, 12d)]
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[TestCase( 8d, 8d)]
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[TestCase( 12d, -3d)]
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[TestCase( 12d, 6d)]
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[TestCase( 20d, 5d)]
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public void Misc3(double A, double B)
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{
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// 1 / ((1 / A + 1 / B) ^ 2) = 16
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/*
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FMOV D2, 1.0e+0
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FDIV D0, D2, D0
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FDIV D1, D2, D1
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FADD D0, D0, D1
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FDIV D0, D2, D0
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FMUL D0, D0, D0
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BRK #0
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RET
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*/
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SetThreadState(V0: new AVec { D0 = A }, V1: new AVec { D0 = B });
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Opcode(0x1E6E1002);
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Opcode(0x1E601840);
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Opcode(0x1E611841);
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Opcode(0x1E612800);
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Opcode(0x1E601840);
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Opcode(0x1E600800);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetThreadState().V0.D0, Is.EqualTo(16d));
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}
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[Test]
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public void MiscF([Range(0u, 92u, 1u)] uint A)
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{
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ulong F_n(uint n)
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{
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ulong a = 0, b = 1, c;
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if (n == 0)
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{
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return a;
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}
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for (uint i = 2; i <= n; i++)
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{
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c = a + b;
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a = b;
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b = c;
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}
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return b;
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}
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/*
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0x0000000000000000: MOV W4, W0
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0x0000000000000004: CBZ W0, #0x3C
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0x0000000000000008: CMP W0, #1
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0x000000000000000C: B.LS #0x48
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0x0000000000000010: MOVZ W2, #0x2
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0x0000000000000014: MOVZ X1, #0x1
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0x0000000000000018: MOVZ X3, #0
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0x000000000000001C: ADD X0, X3, X1
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0x0000000000000020: ADD W2, W2, #1
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0x0000000000000024: MOV X3, X1
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0x0000000000000028: MOV X1, X0
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0x000000000000002C: CMP W4, W2
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0x0000000000000030: B.HS #0x1C
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0x0000000000000034: BRK #0
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0x0000000000000038: RET
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0x000000000000003C: MOVZ X0, #0
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0x0000000000000040: BRK #0
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0x0000000000000044: RET
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0x0000000000000048: MOVZ X0, #0x1
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0x000000000000004C: BRK #0
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0x0000000000000050: RET
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*/
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SetThreadState(X0: A);
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Opcode(0x2A0003E4);
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Opcode(0x340001C0);
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Opcode(0x7100041F);
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Opcode(0x540001E9);
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Opcode(0x52800042);
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Opcode(0xD2800021);
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Opcode(0xD2800003);
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Opcode(0x8B010060);
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Opcode(0x11000442);
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Opcode(0xAA0103E3);
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Opcode(0xAA0003E1);
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Opcode(0x6B02009F);
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Opcode(0x54FFFF62);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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Opcode(0xD2800000);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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Opcode(0xD2800020);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetThreadState().X0, Is.EqualTo(F_n(A)));
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}
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[Test]
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public void MiscR()
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{
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const ulong Result = 5;
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/*
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0x0000000000000000: MOV X0, #2
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0x0000000000000004: MOV X1, #3
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0x0000000000000008: ADD X0, X0, X1
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0x000000000000000C: BRK #0
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0x0000000000000010: RET
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*/
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Opcode(0xD2800040);
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Opcode(0xD2800061);
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Opcode(0x8B010000);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetThreadState().X0, Is.EqualTo(Result));
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Reset();
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/*
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0x0000000000000000: MOV X0, #3
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0x0000000000000004: MOV X1, #2
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0x0000000000000008: ADD X0, X0, X1
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0x000000000000000C: BRK #0
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0x0000000000000010: RET
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*/
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Opcode(0xD2800060);
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Opcode(0xD2800041);
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Opcode(0x8B010000);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetThreadState().X0, Is.EqualTo(Result));
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}
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[TestCase( 0ul)]
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[TestCase( 1ul)]
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[TestCase( 2ul)]
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[TestCase(42ul)]
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public void SanityCheck(ulong A)
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{
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uint Opcode = 0xD503201F; // NOP
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AThreadState ThreadState = SingleOpcode(Opcode, X0: A);
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Assert.That(ThreadState.X0, Is.EqualTo(A));
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}
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}
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}
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