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* Decoders: Add InITBlock argument * OpCodeTable: Minor cleanup * OpCodeTable: Remove existing thumb instruction implementations * OpCodeTable: Prepare for thumb instructions * OpCodeTables: Improve thumb fast lookup * Tests: Prepare for thumb tests * T16: Implement BX * T16: Implement LSL/LSR/ASR (imm) * T16: Implement ADDS, SUBS (reg) * T16: Implement ADDS, SUBS (3-bit immediate) * T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate) * T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers) * T16: Implement ADD, CMP, MOV (high reg) * T16: Implement BLX (reg) * T16: Implement LDR (literal) * T16: Implement {LDR,STR}{,H,B,SB,SH} (register) * T16: Implement {LDR,STR}{,B,H} (immediate) * T16: Implement LDR/STR (SP) * T16: Implement ADR * T16: Implement Add to SP (immediate) * T16: Implement ADD/SUB (SP) * T16: Implement SXTH, SXTB, UXTH, UTXB * T16: Implement CBZ, CBNZ * T16: Implement PUSH, POP * T16: Implement REV, REV16, REVSH * T16: Implement NOP * T16: Implement LDM, STM * T16: Implement SVC * T16: Implement B (conditional) * T16: Implement B (unconditional) * T16: Implement IT * fixup! T16: Implement ADD/SUB (SP) * fixup! T16: Implement Add to SP (immediate) * fixup! T16: Implement IT * CpuTestThumb: Add randomized tests * Remove inITBlock argument * Address nits * Use index to handle IfThenBlockState * Reduce line noise * fixup * nit
111 lines
3.3 KiB
C#
111 lines
3.3 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitFlowHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void B(ArmEmitterContext context)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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context.Branch(context.GetLabel((ulong)op.Immediate));
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}
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public static void Bl(ArmEmitterContext context)
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{
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Blx(context, x: false);
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}
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public static void Blx(ArmEmitterContext context)
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{
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Blx(context, x: true);
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}
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private static void Blx(ArmEmitterContext context, bool x)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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uint pc = op.GetPc();
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bool isThumb = IsThumb(context.CurrOp);
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uint currentPc = isThumb
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? pc | 1
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: pc - 4;
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SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
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// If x is true, then this is a branch with link and exchange.
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// In this case we need to swap the mode between Arm <-> Thumb.
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if (x)
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{
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SetFlag(context, PState.TFlag, Const(isThumb ? 0 : 1));
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}
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EmitCall(context, (ulong)op.Immediate);
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}
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public static void Blxr(ArmEmitterContext context)
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{
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IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
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uint pc = op.GetPc();
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Operand addr = context.Copy(GetIntA32(context, op.Rm));
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Operand bitOne = context.BitwiseAnd(addr, Const(1));
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bool isThumb = IsThumb(context.CurrOp);
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uint currentPc = isThumb
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? (pc - 2) | 1
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: pc - 4;
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SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
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SetFlag(context, PState.TFlag, bitOne);
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EmitVirtualCall(context, addr);
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}
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public static void Bx(ArmEmitterContext context)
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{
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IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
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EmitBxWritePc(context, GetIntA32(context, op.Rm), op.Rm);
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}
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public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true);
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public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false);
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private static void EmitCb(ArmEmitterContext context, bool onNotZero)
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{
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OpCodeT16BImmCmp op = (OpCodeT16BImmCmp)context.CurrOp;
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Operand value = GetIntOrZR(context, op.Rn);
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Operand lblTarget = context.GetLabel((ulong)op.Immediate);
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if (onNotZero)
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{
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context.BranchIfTrue(lblTarget, value);
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}
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else
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{
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context.BranchIfFalse(lblTarget, value);
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}
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}
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public static void It(ArmEmitterContext context)
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{
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OpCodeT16IfThen op = (OpCodeT16IfThen)context.CurrOp;
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context.SetIfThenBlockState(op.IfThenBlockConds);
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}
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}
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} |