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https://github.com/Ryujinx/Ryujinx.git
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* Decoders: Add InITBlock argument * OpCodeTable: Minor cleanup * OpCodeTable: Remove existing thumb instruction implementations * OpCodeTable: Prepare for thumb instructions * OpCodeTables: Improve thumb fast lookup * Tests: Prepare for thumb tests * T16: Implement BX * T16: Implement LSL/LSR/ASR (imm) * T16: Implement ADDS, SUBS (reg) * T16: Implement ADDS, SUBS (3-bit immediate) * T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate) * T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers) * T16: Implement ADD, CMP, MOV (high reg) * T16: Implement BLX (reg) * T16: Implement LDR (literal) * T16: Implement {LDR,STR}{,H,B,SB,SH} (register) * T16: Implement {LDR,STR}{,B,H} (immediate) * T16: Implement LDR/STR (SP) * T16: Implement ADR * T16: Implement Add to SP (immediate) * T16: Implement ADD/SUB (SP) * T16: Implement SXTH, SXTB, UXTH, UTXB * T16: Implement CBZ, CBNZ * T16: Implement PUSH, POP * T16: Implement REV, REV16, REVSH * T16: Implement NOP * T16: Implement LDM, STM * T16: Implement SVC * T16: Implement B (conditional) * T16: Implement B (unconditional) * T16: Implement IT * fixup! T16: Implement ADD/SUB (SP) * fixup! T16: Implement Add to SP (immediate) * fixup! T16: Implement IT * CpuTestThumb: Add randomized tests * Remove inITBlock argument * Address nits * Use index to handle IfThenBlockState * Reduce line noise * fixup * nit
265 lines
7.9 KiB
C#
265 lines
7.9 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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private const int ByteSizeLog2 = 0;
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private const int HWordSizeLog2 = 1;
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private const int WordSizeLog2 = 2;
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private const int DWordSizeLog2 = 3;
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[Flags]
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enum AccessType
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{
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Store = 0,
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Signed = 1,
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Load = 2,
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Ordered = 4,
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Exclusive = 8,
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LoadZx = Load,
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LoadSx = Load | Signed,
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}
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public static void Ldm(ArmEmitterContext context)
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{
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IOpCode32MemMult op = (IOpCode32MemMult)context.CurrOp;
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Operand n = GetIntA32(context, op.Rn);
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Operand baseAddress = context.Add(n, Const(op.Offset));
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bool writesToPc = (op.RegisterMask & (1 << RegisterAlias.Aarch32Pc)) != 0;
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bool writeBack = op.PostOffset != 0 && (op.Rn != RegisterAlias.Aarch32Pc || !writesToPc);
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if (writeBack)
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{
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SetIntA32(context, op.Rn, context.Add(n, Const(op.PostOffset)));
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}
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int mask = op.RegisterMask;
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int offset = 0;
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for (int register = 0; mask != 0; mask >>= 1, register++)
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{
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if ((mask & 1) != 0)
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{
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Operand address = context.Add(baseAddress, Const(offset));
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EmitLoadZx(context, address, register, WordSizeLog2);
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offset += 4;
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}
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}
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}
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public static void Ldr(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, WordSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrb(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, ByteSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrd(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, DWordSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrh(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, HWordSizeLog2, AccessType.LoadZx);
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}
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public static void Ldrsb(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, ByteSizeLog2, AccessType.LoadSx);
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}
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public static void Ldrsh(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, HWordSizeLog2, AccessType.LoadSx);
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}
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public static void Stm(ArmEmitterContext context)
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{
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IOpCode32MemMult op = (IOpCode32MemMult)context.CurrOp;
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Operand n = context.Copy(GetIntA32(context, op.Rn));
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Operand baseAddress = context.Add(n, Const(op.Offset));
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int mask = op.RegisterMask;
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int offset = 0;
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for (int register = 0; mask != 0; mask >>= 1, register++)
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{
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if ((mask & 1) != 0)
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{
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Operand address = context.Add(baseAddress, Const(offset));
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EmitStore(context, address, register, WordSizeLog2);
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// Note: If Rn is also specified on the register list,
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// and Rn is the first register on this list, then the
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// value that is written to memory is the unmodified value,
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// before the write back. If it is on the list, but it's
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// not the first one, then the value written to memory
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// varies between CPUs.
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if (offset == 0 && op.PostOffset != 0)
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{
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// Emit write back after the first write.
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SetIntA32(context, op.Rn, context.Add(n, Const(op.PostOffset)));
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}
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offset += 4;
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}
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}
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}
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public static void Str(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, WordSizeLog2, AccessType.Store);
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}
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public static void Strb(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, ByteSizeLog2, AccessType.Store);
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}
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public static void Strd(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, DWordSizeLog2, AccessType.Store);
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}
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public static void Strh(ArmEmitterContext context)
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{
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EmitLoadOrStore(context, HWordSizeLog2, AccessType.Store);
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}
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private static void EmitLoadOrStore(ArmEmitterContext context, int size, AccessType accType)
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{
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IOpCode32Mem op = (IOpCode32Mem)context.CurrOp;
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Operand n = context.Copy(GetIntA32AlignedPC(context, op.Rn));
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Operand m = GetMemM(context, setCarry: false);
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Operand temp = default;
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if (op.Index || op.WBack)
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{
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temp = op.Add
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? context.Add (n, m)
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: context.Subtract(n, m);
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}
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if (op.WBack)
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{
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SetIntA32(context, op.Rn, temp);
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}
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Operand address;
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if (op.Index)
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{
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address = temp;
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}
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else
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{
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address = n;
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}
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if ((accType & AccessType.Load) != 0)
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{
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void Load(int rt, int offs, int loadSize)
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{
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Operand addr = context.Add(address, Const(offs));
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if ((accType & AccessType.Signed) != 0)
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{
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EmitLoadSx32(context, addr, rt, loadSize);
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}
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else
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{
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EmitLoadZx(context, addr, rt, loadSize);
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}
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}
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if (size == DWordSizeLog2)
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{
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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Load(op.Rt, 0, WordSizeLog2);
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Load(op.Rt | 1, 4, WordSizeLog2);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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Load(op.Rt | 1, 0, WordSizeLog2);
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Load(op.Rt, 4, WordSizeLog2);
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context.MarkLabel(lblEnd);
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}
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else
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{
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Load(op.Rt, 0, size);
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}
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}
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else
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{
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void Store(int rt, int offs, int storeSize)
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{
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Operand addr = context.Add(address, Const(offs));
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EmitStore(context, addr, rt, storeSize);
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}
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if (size == DWordSizeLog2)
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{
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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Store(op.Rt, 0, WordSizeLog2);
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Store(op.Rt | 1, 4, WordSizeLog2);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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Store(op.Rt | 1, 0, WordSizeLog2);
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Store(op.Rt, 4, WordSizeLog2);
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context.MarkLabel(lblEnd);
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}
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else
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{
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Store(op.Rt, 0, size);
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}
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}
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}
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public static void Adr(ArmEmitterContext context)
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{
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IOpCode32Adr op = (IOpCode32Adr)context.CurrOp;
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SetIntA32(context, op.Rd, Const(op.Immediate));
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}
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}
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} |