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https://github.com/Ryujinx/Ryujinx.git
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* Implement inline memory load/store exclusive * Fix missing REX prefix on 8-bits CMPXCHG * Increment PTC version due to bugfix * Remove redundant memory checks * Address PR feedback * Increment PPTC version
175 lines
6.5 KiB
C#
175 lines
6.5 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryExHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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[Flags]
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private enum AccessType
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{
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None = 0,
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Ordered = 1,
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Exclusive = 2,
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OrderedEx = Ordered | Exclusive
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}
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public static void Clrex(ArmEmitterContext context)
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{
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EmitClearExclusive(context);
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}
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public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Dsb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Ldar(ArmEmitterContext context) => EmitLdr(context, AccessType.Ordered);
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public static void Ldaxr(ArmEmitterContext context) => EmitLdr(context, AccessType.OrderedEx);
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public static void Ldxr(ArmEmitterContext context) => EmitLdr(context, AccessType.Exclusive);
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public static void Ldxp(ArmEmitterContext context) => EmitLdp(context, AccessType.Exclusive);
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public static void Ldaxp(ArmEmitterContext context) => EmitLdp(context, AccessType.OrderedEx);
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private static void EmitLdr(ArmEmitterContext context, AccessType accType)
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{
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EmitLoadEx(context, accType, pair: false);
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}
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private static void EmitLdp(ArmEmitterContext context, AccessType accType)
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{
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EmitLoadEx(context, accType, pair: true);
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}
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private static void EmitLoadEx(ArmEmitterContext context, AccessType accType, bool pair)
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{
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OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
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bool ordered = (accType & AccessType.Ordered) != 0;
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bool exclusive = (accType & AccessType.Exclusive) != 0;
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if (ordered)
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{
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EmitBarrier(context);
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}
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Operand address = context.Copy(GetIntOrSP(context, op.Rn));
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if (pair)
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{
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// Exclusive loads should be atomic. For pairwise loads, we need to
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// read all the data at once. For a 32-bits pairwise load, we do a
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// simple 64-bits load, for a 128-bits load, we need to call a special
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// method to read 128-bits atomically.
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if (op.Size == 2)
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{
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Operand value = EmitLoadExclusive(context, address, exclusive, 3);
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Operand valueLow = context.ConvertI64ToI32(value);
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valueLow = context.ZeroExtend32(OperandType.I64, valueLow);
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Operand valueHigh = context.ShiftRightUI(value, Const(32));
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SetIntOrZR(context, op.Rt, valueLow);
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SetIntOrZR(context, op.Rt2, valueHigh);
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}
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else if (op.Size == 3)
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{
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Operand value = EmitLoadExclusive(context, address, exclusive, 4);
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Operand valueLow = context.VectorExtract(OperandType.I64, value, 0);
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Operand valueHigh = context.VectorExtract(OperandType.I64, value, 1);
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SetIntOrZR(context, op.Rt, valueLow);
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SetIntOrZR(context, op.Rt2, valueHigh);
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}
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else
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{
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throw new InvalidOperationException($"Invalid load size of {1 << op.Size} bytes.");
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}
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}
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else
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{
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// 8, 16, 32 or 64-bits (non-pairwise) load.
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Operand value = EmitLoadExclusive(context, address, exclusive, op.Size);
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SetIntOrZR(context, op.Rt, value);
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}
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}
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public static void Pfrm(ArmEmitterContext context)
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{
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// Memory Prefetch, execute as no-op.
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}
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public static void Stlr(ArmEmitterContext context) => EmitStr(context, AccessType.Ordered);
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public static void Stlxr(ArmEmitterContext context) => EmitStr(context, AccessType.OrderedEx);
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public static void Stxr(ArmEmitterContext context) => EmitStr(context, AccessType.Exclusive);
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public static void Stxp(ArmEmitterContext context) => EmitStp(context, AccessType.Exclusive);
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public static void Stlxp(ArmEmitterContext context) => EmitStp(context, AccessType.OrderedEx);
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private static void EmitStr(ArmEmitterContext context, AccessType accType)
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{
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EmitStoreEx(context, accType, pair: false);
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}
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private static void EmitStp(ArmEmitterContext context, AccessType accType)
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{
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EmitStoreEx(context, accType, pair: true);
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}
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private static void EmitStoreEx(ArmEmitterContext context, AccessType accType, bool pair)
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{
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OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
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bool ordered = (accType & AccessType.Ordered) != 0;
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bool exclusive = (accType & AccessType.Exclusive) != 0;
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if (ordered)
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{
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EmitBarrier(context);
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}
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Operand address = context.Copy(GetIntOrSP(context, op.Rn));
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Operand t = GetIntOrZR(context, op.Rt);
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if (pair)
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{
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Debug.Assert(op.Size == 2 || op.Size == 3, "Invalid size for pairwise store.");
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Operand t2 = GetIntOrZR(context, op.Rt2);
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Operand value;
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if (op.Size == 2)
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{
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value = context.BitwiseOr(t, context.ShiftLeft(t2, Const(32)));
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}
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else /* if (op.Size == 3) */
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{
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value = context.VectorInsert(context.VectorZero(), t, 0);
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value = context.VectorInsert(value, t2, 1);
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}
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EmitStoreExclusive(context, address, value, exclusive, op.Size + 1, op.Rs, a32: false);
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}
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else
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{
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EmitStoreExclusive(context, address, t, exclusive, op.Size, op.Rs, a32: false);
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}
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}
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private static void EmitBarrier(ArmEmitterContext context)
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{
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// Note: This barrier is most likely not necessary, and probably
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// doesn't make any difference since we need to do a ton of stuff
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// (software MMU emulation) to read or write anything anyway.
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}
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}
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} |