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https://github.com/Ryujinx/Ryujinx.git
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9cb57fb4bb
* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
115 lines
4.3 KiB
C#
115 lines
4.3 KiB
C#
#define Mov
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("Mov")] // Tested: second half of 2018.
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public sealed class CpuTestMov : CpuTest
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{
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#if Mov
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private const int RndCntImm = 2;
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[Test, Pairwise, Description("MOVK <Xd>, #<imm>{, LSL #<shift>}")]
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public void Movk_64bit([Values(0u, 31u)] uint Rd,
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[Random(RndCntImm)] ulong _Xd,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u, 32u, 48u)] uint shift)
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{
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uint Opcode = 0xF2800000; // MOVK X0, #0, LSL #0
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Opcode |= ((Rd & 31) << 0);
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("MOVK <Wd>, #<imm>{, LSL #<shift>}")]
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public void Movk_32bit([Values(0u, 31u)] uint Rd,
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[Random(RndCntImm)] uint _Wd,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u)] uint shift)
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{
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uint Opcode = 0x72800000; // MOVK W0, #0, LSL #0
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Opcode |= ((Rd & 31) << 0);
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("MOVN <Xd>, #<imm>{, LSL #<shift>}")]
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public void Movn_64bit([Values(0u, 31u)] uint Rd,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u, 32u, 48u)] uint shift)
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{
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uint Opcode = 0x92800000; // MOVN X0, #0, LSL #0
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Opcode |= ((Rd & 31) << 0);
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("MOVN <Wd>, #<imm>{, LSL #<shift>}")]
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public void Movn_32bit([Values(0u, 31u)] uint Rd,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u)] uint shift)
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{
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uint Opcode = 0x12800000; // MOVN W0, #0, LSL #0
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Opcode |= ((Rd & 31) << 0);
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X31: _W31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("MOVZ <Xd>, #<imm>{, LSL #<shift>}")]
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public void Movz_64bit([Values(0u, 31u)] uint Rd,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u, 32u, 48u)] uint shift)
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{
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uint Opcode = 0xD2800000; // MOVZ X0, #0, LSL #0
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Opcode |= ((Rd & 31) << 0);
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X31: _X31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("MOVZ <Wd>, #<imm>{, LSL #<shift>}")]
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public void Movz_32bit([Values(0u, 31u)] uint Rd,
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[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
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[Values(0u, 16u)] uint shift)
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{
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uint Opcode = 0x52800000; // MOVZ W0, #0, LSL #0
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Opcode |= ((Rd & 31) << 0);
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Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X31: _W31);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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