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* Change naming convention for Ryujinx project * Change naming convention for ChocolArm64 project * Fix NaN * Remove unneeded this. from Ryujinx project * Adjust naming from new PRs * Name changes based on feedback * How did this get removed? * Rebasing fix * Change FP enum case * Remove prefix from ChocolArm64 classes - Part 1 * Remove prefix from ChocolArm64 classes - Part 2 * Fix alignment from last commit's renaming * Rename namespaces * Rename stragglers * Fix alignment * Rename OpCode class * Missed a few * Adjust alignment
148 lines
5.9 KiB
C#
148 lines
5.9 KiB
C#
// https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf
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using ChocolArm64.State;
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using NUnit.Framework;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestSimdCrypto : CpuTest
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{
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[Test, Description("AESD <Vd>.16B, <Vn>.16B")]
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public void Aesd_V([Values(0u)] uint Rd,
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[Values(1u)] uint Rn,
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[Values(0x7B5B546573745665ul)] ulong ValueH,
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[Values(0x63746F725D53475Dul)] ulong ValueL,
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[Random(2)] ulong RoundKeyH,
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[Random(2)] ulong RoundKeyL,
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[Values(0x8DCAB9BC035006BCul)] ulong ResultH,
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[Values(0x8F57161E00CAFD8Dul)] ulong ResultL)
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{
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uint Opcode = 0x4E285800; // AESD V0.16B, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH);
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Vector128<float> V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH);
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CpuThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(ResultL));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(ResultH));
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});
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL));
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Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH));
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});
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CompareAgainstUnicorn();
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}
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[Test, Description("AESE <Vd>.16B, <Vn>.16B")]
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public void Aese_V([Values(0u)] uint Rd,
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[Values(1u)] uint Rn,
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[Values(0x7B5B546573745665ul)] ulong ValueH,
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[Values(0x63746F725D53475Dul)] ulong ValueL,
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[Random(2)] ulong RoundKeyH,
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[Random(2)] ulong RoundKeyL,
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[Values(0x8F92A04DFBED204Dul)] ulong ResultH,
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[Values(0x4C39B1402192A84Cul)] ulong ResultL)
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{
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uint Opcode = 0x4E284800; // AESE V0.16B, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH);
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Vector128<float> V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH);
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CpuThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(ResultL));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(ResultH));
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});
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL));
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Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH));
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});
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CompareAgainstUnicorn();
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}
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[Test, Description("AESIMC <Vd>.16B, <Vn>.16B")]
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public void Aesimc_V([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(0x8DCAB9DC035006BCul)] ulong ValueH,
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[Values(0x8F57161E00CAFD8Dul)] ulong ValueL,
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[Values(0xD635A667928B5EAEul)] ulong ResultH,
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[Values(0xEEC9CC3BC55F5777ul)] ulong ResultL)
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{
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uint Opcode = 0x4E287800; // AESIMC V0.16B, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V = MakeVectorE0E1(ValueL, ValueH);
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CpuThreadState ThreadState = SingleOpcode(
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Opcode,
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V0: Rn == 0u ? V : default(Vector128<float>),
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V1: Rn == 1u ? V : default(Vector128<float>));
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(ResultL));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(ResultH));
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});
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if (Rn == 1u)
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{
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(ValueL));
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Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH));
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});
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}
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CompareAgainstUnicorn();
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}
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[Test, Description("AESMC <Vd>.16B, <Vn>.16B")]
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public void Aesmc_V([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(0x627A6F6644B109C8ul)] ulong ValueH,
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[Values(0x2B18330A81C3B3E5ul)] ulong ValueL,
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[Values(0x7B5B546573745665ul)] ulong ResultH,
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[Values(0x63746F725D53475Dul)] ulong ResultL)
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{
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uint Opcode = 0x4E286800; // AESMC V0.16B, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V = MakeVectorE0E1(ValueL, ValueH);
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CpuThreadState ThreadState = SingleOpcode(
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Opcode,
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V0: Rn == 0u ? V : default(Vector128<float>),
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V1: Rn == 1u ? V : default(Vector128<float>));
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(ResultL));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(ResultH));
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});
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if (Rn == 1u)
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{
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(ValueL));
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Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH));
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});
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}
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CompareAgainstUnicorn();
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}
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}
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}
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