Ryujinx/ARMeilleure/Instructions/InstEmitBfm.cs
gdkchan a731ab3a2a Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 21:56:22 +03:00

196 lines
6 KiB
C#

using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
namespace ARMeilleure.Instructions
{
static partial class InstEmit
{
public static void Bfm(ArmEmitterContext context)
{
OpCodeBfm op = (OpCodeBfm)context.CurrOp;
Operand d = GetIntOrZR(context, op.Rd);
Operand n = GetIntOrZR(context, op.Rn);
Operand res;
if (op.Pos < op.Shift)
{
// BFI.
int shift = op.GetBitsCount() - op.Shift;
int width = op.Pos + 1;
long mask = (long)(ulong.MaxValue >> (64 - width));
res = context.ShiftLeft(context.BitwiseAnd(n, Const(n.Type, mask)), Const(shift));
res = context.BitwiseOr(res, context.BitwiseAnd(d, Const(d.Type, ~(mask << shift))));
}
else
{
// BFXIL.
int shift = op.Shift;
int width = op.Pos - shift + 1;
long mask = (long)(ulong.MaxValue >> (64 - width));
res = context.BitwiseAnd(context.ShiftRightUI(n, Const(shift)), Const(n.Type, mask));
res = context.BitwiseOr(res, context.BitwiseAnd(d, Const(d.Type, ~mask)));
}
SetIntOrZR(context, op.Rd, res);
}
public static void Sbfm(ArmEmitterContext context)
{
OpCodeBfm op = (OpCodeBfm)context.CurrOp;
int bitsCount = op.GetBitsCount();
if (op.Pos + 1 == bitsCount)
{
EmitSbfmShift(context);
}
else if (op.Pos < op.Shift)
{
EmitSbfiz(context);
}
else if (op.Pos == 7 && op.Shift == 0)
{
Operand n = GetIntOrZR(context, op.Rn);
SetIntOrZR(context, op.Rd, context.SignExtend8(n.Type, n));
}
else if (op.Pos == 15 && op.Shift == 0)
{
Operand n = GetIntOrZR(context, op.Rn);
SetIntOrZR(context, op.Rd, context.SignExtend16(n.Type, n));
}
else if (op.Pos == 31 && op.Shift == 0)
{
Operand n = GetIntOrZR(context, op.Rn);
SetIntOrZR(context, op.Rd, context.SignExtend32(n.Type, n));
}
else
{
Operand res = GetIntOrZR(context, op.Rn);
res = context.ShiftLeft (res, Const(bitsCount - 1 - op.Pos));
res = context.ShiftRightSI(res, Const(bitsCount - 1));
res = context.BitwiseAnd (res, Const(res.Type, ~op.TMask));
Operand n2 = GetBfmN(context);
SetIntOrZR(context, op.Rd, context.BitwiseOr(res, n2));
}
}
public static void Ubfm(ArmEmitterContext context)
{
OpCodeBfm op = (OpCodeBfm)context.CurrOp;
if (op.Pos + 1 == op.GetBitsCount())
{
EmitUbfmShift(context);
}
else if (op.Pos < op.Shift)
{
EmitUbfiz(context);
}
else if (op.Pos + 1 == op.Shift)
{
EmitBfmLsl(context);
}
else if (op.Pos == 7 && op.Shift == 0)
{
Operand n = GetIntOrZR(context, op.Rn);
SetIntOrZR(context, op.Rd, context.BitwiseAnd(n, Const(n.Type, 0xff)));
}
else if (op.Pos == 15 && op.Shift == 0)
{
Operand n = GetIntOrZR(context, op.Rn);
SetIntOrZR(context, op.Rd, context.BitwiseAnd(n, Const(n.Type, 0xffff)));
}
else
{
SetIntOrZR(context, op.Rd, GetBfmN(context));
}
}
private static void EmitSbfiz(ArmEmitterContext context) => EmitBfiz(context, signed: true);
private static void EmitUbfiz(ArmEmitterContext context) => EmitBfiz(context, signed: false);
private static void EmitBfiz(ArmEmitterContext context, bool signed)
{
OpCodeBfm op = (OpCodeBfm)context.CurrOp;
int width = op.Pos + 1;
Operand res = GetIntOrZR(context, op.Rn);
res = context.ShiftLeft(res, Const(op.GetBitsCount() - width));
res = signed
? context.ShiftRightSI(res, Const(op.Shift - width))
: context.ShiftRightUI(res, Const(op.Shift - width));
SetIntOrZR(context, op.Rd, res);
}
private static void EmitSbfmShift(ArmEmitterContext context)
{
EmitBfmShift(context, signed: true);
}
private static void EmitUbfmShift(ArmEmitterContext context)
{
EmitBfmShift(context, signed: false);
}
private static void EmitBfmShift(ArmEmitterContext context, bool signed)
{
OpCodeBfm op = (OpCodeBfm)context.CurrOp;
Operand res = GetIntOrZR(context, op.Rn);
res = signed
? context.ShiftRightSI(res, Const(op.Shift))
: context.ShiftRightUI(res, Const(op.Shift));
SetIntOrZR(context, op.Rd, res);
}
private static void EmitBfmLsl(ArmEmitterContext context)
{
OpCodeBfm op = (OpCodeBfm)context.CurrOp;
Operand res = GetIntOrZR(context, op.Rn);
int shift = op.GetBitsCount() - op.Shift;
SetIntOrZR(context, op.Rd, context.ShiftLeft(res, Const(shift)));
}
private static Operand GetBfmN(ArmEmitterContext context)
{
OpCodeBfm op = (OpCodeBfm)context.CurrOp;
Operand res = GetIntOrZR(context, op.Rn);
long mask = op.WMask & op.TMask;
return context.BitwiseAnd(context.RotateRight(res, Const(op.Shift)), Const(res.Type, mask));
}
}
}