mirror of
https://github.com/Ryujinx/Ryujinx.git
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905a191e28
* unicorn: Add modified ver of unicorns const gen * unicorn: Use upstream consts These consts were generated from the dev branch of unicorn * unicorn: Split common consts into multiple enums * unicorn: Remove arch prefix from consts * unicorn: Add new windows dll Windows 10 - MSVC x64 shared build * unicorn: Use absolute path for const generation * unicorn: Remove fspcr patch * unicorn: Fix using the wrong file extension For some reason _NativeLibraryExtension evaluates to ".so" even on Windows. * unicorn: Add linux shared object again * unicron: Add DllImportResolver * unicorn: Try to import unicorn using an absolute path * unicorn: Add clean target * unicorn: Replace IsUnicornAvailable() methods * unicorn: Skip tests instead of silently passing them if unicorn is missing * unicorn: Write error message to stderr * unicorn: Make Interface static * unicron: Include prefixed unicorn libs (libunicorn.so) Co-authored-by: merry <git@mary.rs> * unicorn: Add lib prefix to shared object for linux Co-authored-by: merry <git@mary.rs>
341 lines
7.6 KiB
C#
341 lines
7.6 KiB
C#
// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
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// ReSharper disable InconsistentNaming
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namespace Ryujinx.Tests.Unicorn.Native.Const
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{
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public enum Arm64
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{
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// ARM64 CPU
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CPU_ARM64_A57 = 0,
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CPU_ARM64_A53 = 1,
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CPU_ARM64_A72 = 2,
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CPU_ARM64_MAX = 3,
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CPU_ARM64_ENDING = 4,
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// ARM64 registers
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REG_INVALID = 0,
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REG_X29 = 1,
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REG_X30 = 2,
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REG_NZCV = 3,
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REG_SP = 4,
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REG_WSP = 5,
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REG_WZR = 6,
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REG_XZR = 7,
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REG_B0 = 8,
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REG_B1 = 9,
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REG_B2 = 10,
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REG_B3 = 11,
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REG_B4 = 12,
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REG_B5 = 13,
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REG_B6 = 14,
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REG_B7 = 15,
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REG_B8 = 16,
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REG_B9 = 17,
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REG_B10 = 18,
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REG_B11 = 19,
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REG_B12 = 20,
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REG_B13 = 21,
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REG_B14 = 22,
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REG_B15 = 23,
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REG_B16 = 24,
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REG_B17 = 25,
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REG_B18 = 26,
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REG_B19 = 27,
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REG_B20 = 28,
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REG_B21 = 29,
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REG_B22 = 30,
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REG_B23 = 31,
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REG_B24 = 32,
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REG_B25 = 33,
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REG_B26 = 34,
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REG_B27 = 35,
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REG_B28 = 36,
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REG_B29 = 37,
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REG_B30 = 38,
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REG_B31 = 39,
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REG_D0 = 40,
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REG_D1 = 41,
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REG_D2 = 42,
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REG_D3 = 43,
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REG_D4 = 44,
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REG_D5 = 45,
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REG_D6 = 46,
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REG_D7 = 47,
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REG_D8 = 48,
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REG_D9 = 49,
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REG_D10 = 50,
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REG_D11 = 51,
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REG_D12 = 52,
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REG_D13 = 53,
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REG_D14 = 54,
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REG_D15 = 55,
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REG_D16 = 56,
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REG_D17 = 57,
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REG_D18 = 58,
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REG_D19 = 59,
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REG_D20 = 60,
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REG_D21 = 61,
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REG_D22 = 62,
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REG_D23 = 63,
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REG_D24 = 64,
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REG_D25 = 65,
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REG_D26 = 66,
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REG_D27 = 67,
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REG_D28 = 68,
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REG_D29 = 69,
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REG_D30 = 70,
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REG_D31 = 71,
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REG_H0 = 72,
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REG_H1 = 73,
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REG_H2 = 74,
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REG_H3 = 75,
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REG_H4 = 76,
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REG_H5 = 77,
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REG_H6 = 78,
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REG_H7 = 79,
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REG_H8 = 80,
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REG_H9 = 81,
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REG_H10 = 82,
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REG_H11 = 83,
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REG_H12 = 84,
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REG_H13 = 85,
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REG_H14 = 86,
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REG_H15 = 87,
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REG_H16 = 88,
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REG_H17 = 89,
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REG_H18 = 90,
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REG_H19 = 91,
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REG_H20 = 92,
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REG_H21 = 93,
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REG_H22 = 94,
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REG_H23 = 95,
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REG_H24 = 96,
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REG_H25 = 97,
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REG_H26 = 98,
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REG_H27 = 99,
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REG_H28 = 100,
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REG_H29 = 101,
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REG_H30 = 102,
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REG_H31 = 103,
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REG_Q0 = 104,
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REG_Q1 = 105,
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REG_Q2 = 106,
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REG_Q3 = 107,
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REG_Q4 = 108,
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REG_Q5 = 109,
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REG_Q6 = 110,
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REG_Q7 = 111,
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REG_Q8 = 112,
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REG_Q9 = 113,
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REG_Q10 = 114,
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REG_Q11 = 115,
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REG_Q12 = 116,
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REG_Q13 = 117,
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REG_Q14 = 118,
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REG_Q15 = 119,
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REG_Q16 = 120,
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REG_Q17 = 121,
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REG_Q18 = 122,
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REG_Q19 = 123,
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REG_Q20 = 124,
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REG_Q21 = 125,
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REG_Q22 = 126,
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REG_Q23 = 127,
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REG_Q24 = 128,
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REG_Q25 = 129,
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REG_Q26 = 130,
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REG_Q27 = 131,
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REG_Q28 = 132,
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REG_Q29 = 133,
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REG_Q30 = 134,
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REG_Q31 = 135,
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REG_S0 = 136,
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REG_S1 = 137,
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REG_S2 = 138,
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REG_S3 = 139,
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REG_S4 = 140,
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REG_S5 = 141,
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REG_S6 = 142,
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REG_S7 = 143,
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REG_S8 = 144,
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REG_S9 = 145,
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REG_S10 = 146,
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REG_S11 = 147,
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REG_S12 = 148,
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REG_S13 = 149,
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REG_S14 = 150,
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REG_S15 = 151,
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REG_S16 = 152,
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REG_S17 = 153,
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REG_S18 = 154,
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REG_S19 = 155,
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REG_S20 = 156,
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REG_S21 = 157,
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REG_S22 = 158,
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REG_S23 = 159,
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REG_S24 = 160,
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REG_S25 = 161,
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REG_S26 = 162,
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REG_S27 = 163,
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REG_S28 = 164,
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REG_S29 = 165,
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REG_S30 = 166,
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REG_S31 = 167,
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REG_W0 = 168,
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REG_W1 = 169,
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REG_W2 = 170,
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REG_W3 = 171,
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REG_W4 = 172,
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REG_W5 = 173,
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REG_W6 = 174,
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REG_W7 = 175,
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REG_W8 = 176,
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REG_W9 = 177,
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REG_W10 = 178,
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REG_W11 = 179,
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REG_W12 = 180,
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REG_W13 = 181,
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REG_W14 = 182,
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REG_W15 = 183,
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REG_W16 = 184,
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REG_W17 = 185,
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REG_W18 = 186,
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REG_W19 = 187,
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REG_W20 = 188,
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REG_W21 = 189,
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REG_W22 = 190,
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REG_W23 = 191,
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REG_W24 = 192,
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REG_W25 = 193,
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REG_W26 = 194,
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REG_W27 = 195,
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REG_W28 = 196,
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REG_W29 = 197,
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REG_W30 = 198,
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REG_X0 = 199,
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REG_X1 = 200,
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REG_X2 = 201,
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REG_X3 = 202,
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REG_X4 = 203,
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REG_X5 = 204,
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REG_X6 = 205,
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REG_X7 = 206,
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REG_X8 = 207,
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REG_X9 = 208,
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REG_X10 = 209,
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REG_X11 = 210,
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REG_X12 = 211,
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REG_X13 = 212,
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REG_X14 = 213,
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REG_X15 = 214,
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REG_X16 = 215,
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REG_X17 = 216,
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REG_X18 = 217,
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REG_X19 = 218,
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REG_X20 = 219,
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REG_X21 = 220,
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REG_X22 = 221,
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REG_X23 = 222,
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REG_X24 = 223,
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REG_X25 = 224,
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REG_X26 = 225,
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REG_X27 = 226,
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REG_X28 = 227,
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REG_V0 = 228,
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REG_V1 = 229,
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REG_V2 = 230,
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REG_V3 = 231,
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REG_V4 = 232,
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REG_V5 = 233,
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REG_V6 = 234,
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REG_V7 = 235,
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REG_V8 = 236,
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REG_V9 = 237,
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REG_V10 = 238,
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REG_V11 = 239,
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REG_V12 = 240,
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REG_V13 = 241,
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REG_V14 = 242,
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REG_V15 = 243,
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REG_V16 = 244,
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REG_V17 = 245,
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REG_V18 = 246,
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REG_V19 = 247,
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REG_V20 = 248,
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REG_V21 = 249,
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REG_V22 = 250,
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REG_V23 = 251,
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REG_V24 = 252,
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REG_V25 = 253,
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REG_V26 = 254,
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REG_V27 = 255,
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REG_V28 = 256,
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REG_V29 = 257,
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REG_V30 = 258,
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REG_V31 = 259,
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// pseudo registers
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REG_PC = 260,
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REG_CPACR_EL1 = 261,
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// thread registers, depreciated, use UC_ARM64_REG_CP_REG instead
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REG_TPIDR_EL0 = 262,
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REG_TPIDRRO_EL0 = 263,
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REG_TPIDR_EL1 = 264,
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REG_PSTATE = 265,
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// exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead
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REG_ELR_EL0 = 266,
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REG_ELR_EL1 = 267,
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REG_ELR_EL2 = 268,
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REG_ELR_EL3 = 269,
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// stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead
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REG_SP_EL0 = 270,
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REG_SP_EL1 = 271,
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REG_SP_EL2 = 272,
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REG_SP_EL3 = 273,
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// other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead
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REG_TTBR0_EL1 = 274,
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REG_TTBR1_EL1 = 275,
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REG_ESR_EL0 = 276,
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REG_ESR_EL1 = 277,
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REG_ESR_EL2 = 278,
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REG_ESR_EL3 = 279,
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REG_FAR_EL0 = 280,
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REG_FAR_EL1 = 281,
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REG_FAR_EL2 = 282,
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REG_FAR_EL3 = 283,
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REG_PAR_EL1 = 284,
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REG_MAIR_EL1 = 285,
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REG_VBAR_EL0 = 286,
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REG_VBAR_EL1 = 287,
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REG_VBAR_EL2 = 288,
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REG_VBAR_EL3 = 289,
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REG_CP_REG = 290,
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// floating point control and status registers
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REG_FPCR = 291,
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REG_FPSR = 292,
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REG_ENDING = 293,
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// alias registers
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REG_IP0 = 215,
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REG_IP1 = 216,
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REG_FP = 1,
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REG_LR = 2,
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// ARM64 instructions
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INS_INVALID = 0,
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INS_MRS = 1,
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INS_MSR = 2,
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INS_SYS = 3,
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INS_SYSL = 4,
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INS_ENDING = 5,
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}
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}
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