mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-20 07:38:42 +02:00
* Initial implementation of buffer flush (VERY WIP) * Host shaders need to be rebuilt for the SSBO write flag. * New approach with reserved regions and gl sync * Fix a ton of buffer issues. * Remove unused buffer unmapped behaviour * Revert "Remove unused buffer unmapped behaviour" This reverts commit f1700e52fb8760180ac5e0987a07d409d1e70ece. * Delete modified ranges on unmap Fixes potential crashes in Super Smash Bros, where a previously modified range could lie on either side of an unmap. * Cache some more delegates. * Dispose Sync on Close * Also create host sync for GPFifo syncpoint increment. * Copy buffer optimization, add docs * Fix race condition with OpenGL Sync * Enable read tracking on CommandBuffer, insert syncpoint on WaitForIdle * Performance: Only flush individual pages of SSBO at a time This avoids flushing large amounts of data when only a small amount is actually used. * Signal Modified rather than flushing after clear * Fix some docs and code style. * Introduce a new test for tracking memory protection. Sucessfully demonstrates that the bug causing write protection to be cleared by a read action has been fixed. (these tests fail on master) * Address Comments * Add host sync for SetReference This ensures that any indirect draws will correctly flush any related buffer data written before them. Fixes some flashing and misplaced world geometry in MH rise. * Make PageAlign static * Re-enable read tracking, for reads.
429 lines
15 KiB
C#
429 lines
15 KiB
C#
using Ryujinx.Memory;
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using Ryujinx.Memory.Range;
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using System;
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using System.Collections.Generic;
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using System.Runtime.CompilerServices;
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using System.Runtime.InteropServices;
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namespace Ryujinx.Graphics.Gpu.Memory
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{
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/// <summary>
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/// GPU memory manager.
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/// </summary>
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public class MemoryManager : IWritableBlock
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{
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private const int PtLvl0Bits = 14;
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private const int PtLvl1Bits = 14;
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public const int PtPageBits = 12;
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private const ulong PtLvl0Size = 1UL << PtLvl0Bits;
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private const ulong PtLvl1Size = 1UL << PtLvl1Bits;
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public const ulong PageSize = 1UL << PtPageBits;
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private const ulong PtLvl0Mask = PtLvl0Size - 1;
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private const ulong PtLvl1Mask = PtLvl1Size - 1;
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public const ulong PageMask = PageSize - 1;
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private const int PtLvl0Bit = PtPageBits + PtLvl1Bits;
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private const int PtLvl1Bit = PtPageBits;
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private const int AddressSpaceBits = PtPageBits + PtLvl1Bits + PtLvl0Bits;
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public const ulong PteUnmapped = 0xffffffff_ffffffff;
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private readonly ulong[][] _pageTable;
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public event EventHandler<UnmapEventArgs> MemoryUnmapped;
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private GpuContext _context;
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/// <summary>
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/// Creates a new instance of the GPU memory manager.
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/// </summary>
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public MemoryManager(GpuContext context)
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{
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_context = context;
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_pageTable = new ulong[PtLvl0Size][];
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}
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/// <summary>
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/// Reads data from GPU mapped memory.
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/// </summary>
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/// <typeparam name="T">Type of the data</typeparam>
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/// <param name="va">GPU virtual address where the data is located</param>
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/// <returns>The data at the specified memory location</returns>
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public T Read<T>(ulong va) where T : unmanaged
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{
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return MemoryMarshal.Cast<byte, T>(GetSpan(va, Unsafe.SizeOf<T>()))[0];
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}
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/// <summary>
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/// Gets a read-only span of data from GPU mapped memory.
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/// </summary>
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/// <param name="va">GPU virtual address where the data is located</param>
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/// <param name="size">Size of the data</param>
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/// <param name="tracked">True if read tracking is triggered on the span</param>
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/// <returns>The span of the data at the specified memory location</returns>
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public ReadOnlySpan<byte> GetSpan(ulong va, int size, bool tracked = false)
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{
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if (IsContiguous(va, size))
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{
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return _context.PhysicalMemory.GetSpan(Translate(va), size, tracked);
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}
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else
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{
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Span<byte> data = new byte[size];
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ReadImpl(va, data, tracked);
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return data;
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}
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}
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/// <summary>
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/// Reads data from a possibly non-contiguous region of GPU mapped memory.
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/// </summary>
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/// <param name="va">GPU virtual address of the data</param>
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/// <param name="data">Span to write the read data into</param>
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/// <param name="tracked">True to enable write tracking on read, false otherwise</param>
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private void ReadImpl(ulong va, Span<byte> data, bool tracked)
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{
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if (data.Length == 0)
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{
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return;
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}
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int offset = 0, size;
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if ((va & PageMask) != 0)
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{
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ulong pa = Translate(va);
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size = Math.Min(data.Length, (int)PageSize - (int)(va & PageMask));
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_context.PhysicalMemory.GetSpan(pa, size, tracked).CopyTo(data.Slice(0, size));
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offset += size;
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}
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for (; offset < data.Length; offset += size)
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{
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ulong pa = Translate(va + (ulong)offset);
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size = Math.Min(data.Length - offset, (int)PageSize);
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_context.PhysicalMemory.GetSpan(pa, size, tracked).CopyTo(data.Slice(offset, size));
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}
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}
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/// <summary>
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/// Gets a writable region from GPU mapped memory.
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/// </summary>
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/// <param name="address">Start address of the range</param>
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/// <param name="size">Size in bytes to be range</param>
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/// <returns>A writable region with the data at the specified memory location</returns>
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public WritableRegion GetWritableRegion(ulong va, int size)
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{
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if (IsContiguous(va, size))
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{
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return _context.PhysicalMemory.GetWritableRegion(Translate(va), size);
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}
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else
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{
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Memory<byte> memory = new byte[size];
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GetSpan(va, size).CopyTo(memory.Span);
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return new WritableRegion(this, va, memory);
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}
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}
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/// <summary>
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/// Writes data to GPU mapped memory.
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/// </summary>
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/// <typeparam name="T">Type of the data</typeparam>
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/// <param name="va">GPU virtual address to write the value into</param>
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/// <param name="value">The value to be written</param>
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public void Write<T>(ulong va, T value) where T : unmanaged
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{
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Write(va, MemoryMarshal.Cast<T, byte>(MemoryMarshal.CreateSpan(ref value, 1)));
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}
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/// <summary>
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/// Writes data to GPU mapped memory.
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/// </summary>
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/// <param name="va">GPU virtual address to write the data into</param>
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/// <param name="data">The data to be written</param>
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public void Write(ulong va, ReadOnlySpan<byte> data)
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{
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WriteImpl(va, data, _context.PhysicalMemory.Write);
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}
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/// <summary>
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/// Writes data to GPU mapped memory without write tracking.
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/// </summary>
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/// <param name="va">GPU virtual address to write the data into</param>
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/// <param name="data">The data to be written</param>
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public void WriteUntracked(ulong va, ReadOnlySpan<byte> data)
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{
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WriteImpl(va, data, _context.PhysicalMemory.WriteUntracked);
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}
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private delegate void WriteCallback(ulong address, ReadOnlySpan<byte> data);
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/// <summary>
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/// Writes data to possibly non-contiguous GPU mapped memory.
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/// </summary>
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/// <param name="va">GPU virtual address of the region to write into</param>
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/// <param name="data">Data to be written</param>
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/// <param name="writeCallback">Write callback</param>
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private void WriteImpl(ulong va, ReadOnlySpan<byte> data, WriteCallback writeCallback)
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{
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if (IsContiguous(va, data.Length))
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{
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writeCallback(Translate(va), data);
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}
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else
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{
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int offset = 0, size;
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if ((va & PageMask) != 0)
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{
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ulong pa = Translate(va);
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size = Math.Min(data.Length, (int)PageSize - (int)(va & PageMask));
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writeCallback(pa, data.Slice(0, size));
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offset += size;
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}
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for (; offset < data.Length; offset += size)
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{
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ulong pa = Translate(va + (ulong)offset);
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size = Math.Min(data.Length - offset, (int)PageSize);
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writeCallback(pa, data.Slice(offset, size));
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}
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}
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}
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/// <summary>
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/// Maps a given range of pages to the specified CPU virtual address.
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/// </summary>
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/// <remarks>
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/// All addresses and sizes must be page aligned.
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/// </remarks>
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/// <param name="pa">CPU virtual address to map into</param>
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/// <param name="va">GPU virtual address to be mapped</param>
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/// <param name="size">Size in bytes of the mapping</param>
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public void Map(ulong pa, ulong va, ulong size)
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{
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lock (_pageTable)
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{
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MemoryUnmapped?.Invoke(this, new UnmapEventArgs(va, size));
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, pa + offset);
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}
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}
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}
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/// <summary>
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/// Unmaps a given range of pages at the specified GPU virtual memory region.
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/// </summary>
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/// <param name="va">GPU virtual address to unmap</param>
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/// <param name="size">Size in bytes of the region being unmapped</param>
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public void Unmap(ulong va, ulong size)
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{
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lock (_pageTable)
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{
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// Event handlers are not expected to be thread safe.
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MemoryUnmapped?.Invoke(this, new UnmapEventArgs(va, size));
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, PteUnmapped);
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}
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}
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}
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/// <summary>
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/// Checks if a region of GPU mapped memory is contiguous.
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/// </summary>
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/// <param name="va">GPU virtual address of the region</param>
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/// <param name="size">Size of the region</param>
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/// <returns>True if the region is contiguous, false otherwise</returns>
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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private bool IsContiguous(ulong va, int size)
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{
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if (!ValidateAddress(va) || GetPte(va) == PteUnmapped)
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{
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return false;
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}
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ulong endVa = (va + (ulong)size + PageMask) & ~PageMask;
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va &= ~PageMask;
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int pages = (int)((endVa - va) / PageSize);
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for (int page = 0; page < pages - 1; page++)
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{
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if (!ValidateAddress(va + PageSize) || GetPte(va + PageSize) == PteUnmapped)
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{
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return false;
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}
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if (Translate(va) + PageSize != Translate(va + PageSize))
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{
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return false;
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}
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va += PageSize;
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}
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return true;
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}
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/// <summary>
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/// Gets the physical regions that make up the given virtual address region.
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/// </summary>
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/// <param name="va">Virtual address of the range</param>
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/// <param name="size">Size of the range</param>
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/// <returns>Multi-range with the physical regions</returns>
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/// <exception cref="InvalidMemoryRegionException">The memory region specified by <paramref name="va"/> and <paramref name="size"/> is not fully mapped</exception>
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public MultiRange GetPhysicalRegions(ulong va, ulong size)
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{
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if (IsContiguous(va, (int)size))
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{
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return new MultiRange(Translate(va), size);
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}
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if (!IsMapped(va))
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{
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throw new InvalidMemoryRegionException($"The specified GPU virtual address 0x{va:X} is not mapped.");
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}
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ulong regionStart = Translate(va);
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ulong regionSize = Math.Min(size, PageSize - (va & PageMask));
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ulong endVa = va + size;
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ulong endVaRounded = (endVa + PageMask) & ~PageMask;
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va &= ~PageMask;
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int pages = (int)((endVaRounded - va) / PageSize);
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var regions = new List<MemoryRange>();
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for (int page = 0; page < pages - 1; page++)
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{
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if (!IsMapped(va + PageSize))
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{
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throw new InvalidMemoryRegionException($"The specified GPU virtual memory range 0x{va:X}..0x{(va + size):X} is not fully mapped.");
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}
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ulong newPa = Translate(va + PageSize);
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if (Translate(va) + PageSize != newPa)
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{
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regions.Add(new MemoryRange(regionStart, regionSize));
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regionStart = newPa;
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regionSize = 0;
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}
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va += PageSize;
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regionSize += Math.Min(endVa - va, PageSize);
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}
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regions.Add(new MemoryRange(regionStart, regionSize));
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return new MultiRange(regions.ToArray());
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}
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/// <summary>
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/// Validates a GPU virtual address.
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/// </summary>
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/// <param name="va">Address to validate</param>
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/// <returns>True if the address is valid, false otherwise</returns>
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private static bool ValidateAddress(ulong va)
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{
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return va < (1UL << AddressSpaceBits);
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}
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/// <summary>
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/// Checks if a given page is mapped.
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/// </summary>
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/// <param name="va">GPU virtual address of the page to check</param>
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/// <returns>True if the page is mapped, false otherwise</returns>
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public bool IsMapped(ulong va)
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{
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return Translate(va) != PteUnmapped;
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}
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/// <summary>
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/// Translates a GPU virtual address to a CPU virtual address.
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/// </summary>
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/// <param name="va">GPU virtual address to be translated</param>
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/// <returns>CPU virtual address, or <see cref="PteUnmapped"/> if unmapped</returns>
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public ulong Translate(ulong va)
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{
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if (!ValidateAddress(va))
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{
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return PteUnmapped;
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}
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ulong baseAddress = GetPte(va);
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if (baseAddress == PteUnmapped)
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{
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return PteUnmapped;
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}
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return baseAddress + (va & PageMask);
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}
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/// <summary>
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/// Gets the Page Table entry for a given GPU virtual address.
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/// </summary>
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/// <param name="va">GPU virtual address</param>
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/// <returns>Page table entry (CPU virtual address)</returns>
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private ulong GetPte(ulong va)
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{
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ulong l0 = (va >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (va >> PtLvl1Bit) & PtLvl1Mask;
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if (_pageTable[l0] == null)
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{
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return PteUnmapped;
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}
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return _pageTable[l0][l1];
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}
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/// <summary>
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/// Sets a Page Table entry at a given GPU virtual address.
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/// </summary>
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/// <param name="va">GPU virtual address</param>
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/// <param name="pte">Page table entry (CPU virtual address)</param>
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private void SetPte(ulong va, ulong pte)
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{
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ulong l0 = (va >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (va >> PtLvl1Bit) & PtLvl1Mask;
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if (_pageTable[l0] == null)
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{
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_pageTable[l0] = new ulong[PtLvl1Size];
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for (ulong index = 0; index < PtLvl1Size; index++)
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{
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_pageTable[l0][index] = PteUnmapped;
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}
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}
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_pageTable[l0][l1] = pte;
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}
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}
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} |