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https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
168 lines
5 KiB
C#
168 lines
5 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Collections.Generic;
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using System.Text;
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namespace ARMeilleure.Diagnostics
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{
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static class IRDumper
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{
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private const string Indentation = " ";
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public static string GetDump(ControlFlowGraph cfg)
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{
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StringBuilder sb = new StringBuilder();
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Dictionary<Operand, string> localNames = new Dictionary<Operand, string>();
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string indentation = string.Empty;
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void IncreaseIndentation()
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{
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indentation += Indentation;
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}
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void DecreaseIndentation()
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{
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indentation = indentation.Substring(0, indentation.Length - Indentation.Length);
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}
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void AppendLine(string text)
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{
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sb.AppendLine(indentation + text);
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}
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IncreaseIndentation();
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foreach (BasicBlock block in cfg.Blocks)
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{
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string blockName = GetBlockName(block);
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if (block.Next != null)
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{
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blockName += $" (next {GetBlockName(block.Next)})";
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}
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if (block.Branch != null)
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{
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blockName += $" (branch {GetBlockName(block.Branch)})";
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}
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blockName += ":";
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AppendLine(blockName);
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IncreaseIndentation();
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foreach (Node node in block.Operations)
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{
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string[] sources = new string[node.SourcesCount];
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string instName = string.Empty;
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if (node is PhiNode phi)
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{
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for (int index = 0; index < sources.Length; index++)
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{
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string phiBlockName = GetBlockName(phi.GetBlock(index));
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string operName = GetOperandName(phi.GetSource(index), localNames);
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sources[index] = $"({phiBlockName}: {operName})";
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}
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instName = "Phi";
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}
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else if (node is Operation operation)
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{
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for (int index = 0; index < sources.Length; index++)
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{
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sources[index] = GetOperandName(operation.GetSource(index), localNames);
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}
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instName = operation.Instruction.ToString();
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}
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string allSources = string.Join(", ", sources);
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string line = instName + " " + allSources;
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if (node.Destination != null)
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{
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line = GetOperandName(node.Destination, localNames) + " = " + line;
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}
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AppendLine(line);
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}
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DecreaseIndentation();
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}
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return sb.ToString();
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}
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private static string GetBlockName(BasicBlock block)
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{
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return $"block{block.Index}";
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}
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private static string GetOperandName(Operand operand, Dictionary<Operand, string> localNames)
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{
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if (operand == null)
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{
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return "<NULL>";
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}
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string name = string.Empty;
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if (operand.Kind == OperandKind.LocalVariable)
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{
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if (!localNames.TryGetValue(operand, out string localName))
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{
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localName = "%" + localNames.Count;
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localNames.Add(operand, localName);
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}
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name = localName;
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}
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else if (operand.Kind == OperandKind.Register)
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{
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Register reg = operand.GetRegister();
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switch (reg.Type)
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{
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case RegisterType.Flag: name = "b" + reg.Index; break;
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case RegisterType.Integer: name = "r" + reg.Index; break;
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case RegisterType.Vector: name = "v" + reg.Index; break;
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}
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}
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else if (operand.Kind == OperandKind.Constant)
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{
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name = "0x" + operand.Value.ToString("X");
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}
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else
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{
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name = operand.Kind.ToString().ToLower();
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}
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return GetTypeName(operand.Type) + " " + name;
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}
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private static string GetTypeName(OperandType type)
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{
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switch (type)
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{
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case OperandType.FP32: return "f32";
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case OperandType.FP64: return "f64";
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case OperandType.I32: return "i32";
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case OperandType.I64: return "i64";
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case OperandType.None: return "none";
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case OperandType.V128: return "v128";
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}
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throw new ArgumentException($"Invalid operand type \"{type}\".");
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}
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}
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} |