mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-10 17:58:50 +02:00
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
369 lines
11 KiB
C#
369 lines
11 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitAluHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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public static void Adc(ArmEmitterContext context) => EmitAdc(context, setFlags: false);
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public static void Adcs(ArmEmitterContext context) => EmitAdc(context, setFlags: true);
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private static void EmitAdc(ArmEmitterContext context, bool setFlags)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand d = context.Add(n, m);
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Operand carry = GetFlag(PState.CFlag);
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if (context.CurrOp.RegisterSize == RegisterSize.Int64)
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{
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carry = context.ZeroExtend32(OperandType.I64, carry);
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}
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d = context.Add(d, carry);
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if (setFlags)
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{
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EmitNZFlagsCheck(context, d);
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EmitAdcsCCheck(context, n, d);
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EmitAddsVCheck(context, n, m, d);
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}
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SetAluDOrZR(context, d);
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}
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public static void Add(ArmEmitterContext context)
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{
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SetAluD(context, context.Add(GetAluN(context), GetAluM(context)));
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}
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public static void Adds(ArmEmitterContext context)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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context.MarkComparison(n, m);
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Operand d = context.Add(n, m);
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EmitNZFlagsCheck(context, d);
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EmitAddsCCheck(context, n, d);
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EmitAddsVCheck(context, n, m, d);
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SetAluDOrZR(context, d);
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}
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public static void And(ArmEmitterContext context)
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{
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SetAluD(context, context.BitwiseAnd(GetAluN(context), GetAluM(context)));
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}
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public static void Ands(ArmEmitterContext context)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand d = context.BitwiseAnd(n, m);
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EmitNZFlagsCheck(context, d);
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EmitCVFlagsClear(context);
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SetAluDOrZR(context, d);
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}
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public static void Asrv(ArmEmitterContext context)
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{
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SetAluDOrZR(context, context.ShiftRightSI(GetAluN(context), GetAluMShift(context)));
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}
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public static void Bic(ArmEmitterContext context) => EmitBic(context, setFlags: false);
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public static void Bics(ArmEmitterContext context) => EmitBic(context, setFlags: true);
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private static void EmitBic(ArmEmitterContext context, bool setFlags)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand d = context.BitwiseAnd(n, context.BitwiseNot(m));
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if (setFlags)
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{
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EmitNZFlagsCheck(context, d);
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EmitCVFlagsClear(context);
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}
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SetAluD(context, d, setFlags);
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}
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public static void Cls(ArmEmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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Operand nHigh = context.ShiftRightUI(n, Const(1));
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bool is32Bits = op.RegisterSize == RegisterSize.Int32;
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Operand mask = is32Bits ? Const(int.MaxValue) : Const(long.MaxValue);
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Operand nLow = context.BitwiseAnd(n, mask);
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Operand res = context.CountLeadingZeros(context.BitwiseExclusiveOr(nHigh, nLow));
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res = context.Subtract(res, Const(res.Type, 1));
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SetAluDOrZR(context, res);
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}
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public static void Clz(ArmEmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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Operand d = context.CountLeadingZeros(n);
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SetAluDOrZR(context, d);
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}
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public static void Eon(ArmEmitterContext context)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand d = context.BitwiseExclusiveOr(n, context.BitwiseNot(m));
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SetAluD(context, d);
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}
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public static void Eor(ArmEmitterContext context)
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{
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SetAluD(context, context.BitwiseExclusiveOr(GetAluN(context), GetAluM(context)));
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}
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public static void Extr(ArmEmitterContext context)
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{
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OpCodeAluRs op = (OpCodeAluRs)context.CurrOp;
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Operand res = GetIntOrZR(context, op.Rm);
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if (op.Shift != 0)
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{
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if (op.Rn == op.Rm)
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{
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res = context.RotateRight(res, Const(op.Shift));
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}
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else
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{
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res = context.ShiftRightUI(res, Const(op.Shift));
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Operand n = GetIntOrZR(context, op.Rn);
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int invShift = op.GetBitsCount() - op.Shift;
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res = context.BitwiseOr(res, context.ShiftLeft(n, Const(invShift)));
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}
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}
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SetAluDOrZR(context, res);
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}
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public static void Lslv(ArmEmitterContext context)
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{
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SetAluDOrZR(context, context.ShiftLeft(GetAluN(context), GetAluMShift(context)));
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}
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public static void Lsrv(ArmEmitterContext context)
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{
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SetAluDOrZR(context, context.ShiftRightUI(GetAluN(context), GetAluMShift(context)));
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}
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public static void Sbc(ArmEmitterContext context) => EmitSbc(context, setFlags: false);
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public static void Sbcs(ArmEmitterContext context) => EmitSbc(context, setFlags: true);
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private static void EmitSbc(ArmEmitterContext context, bool setFlags)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand d = context.Subtract(n, m);
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Operand borrow = context.BitwiseExclusiveOr(GetFlag(PState.CFlag), Const(1));
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if (context.CurrOp.RegisterSize == RegisterSize.Int64)
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{
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borrow = context.ZeroExtend32(OperandType.I64, borrow);
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}
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d = context.Subtract(d, borrow);
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if (setFlags)
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{
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EmitNZFlagsCheck(context, d);
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EmitSbcsCCheck(context, n, m);
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EmitSubsVCheck(context, n, m, d);
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}
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SetAluDOrZR(context, d);
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}
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public static void Sub(ArmEmitterContext context)
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{
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SetAluD(context, context.Subtract(GetAluN(context), GetAluM(context)));
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}
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public static void Subs(ArmEmitterContext context)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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context.MarkComparison(n, m);
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Operand d = context.Subtract(n, m);
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EmitNZFlagsCheck(context, d);
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EmitSubsCCheck(context, n, m);
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EmitSubsVCheck(context, n, m, d);
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SetAluDOrZR(context, d);
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}
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public static void Orn(ArmEmitterContext context)
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{
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Operand n = GetAluN(context);
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Operand m = GetAluM(context);
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Operand d = context.BitwiseOr(n, context.BitwiseNot(m));
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SetAluD(context, d);
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}
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public static void Orr(ArmEmitterContext context)
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{
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SetAluD(context, context.BitwiseOr(GetAluN(context), GetAluM(context)));
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}
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public static void Rbit(ArmEmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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Operand d;
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if (op.RegisterSize == RegisterSize.Int32)
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{
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d = context.Call(new _U32_U32(SoftFallback.ReverseBits32), n);
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}
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else
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{
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d = context.Call(new _U64_U64(SoftFallback.ReverseBits64), n);
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}
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SetAluDOrZR(context, d);
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}
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public static void Rev16(ArmEmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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Operand d;
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if (op.RegisterSize == RegisterSize.Int32)
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{
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d = context.Call(new _U32_U32(SoftFallback.ReverseBytes16_32), n);
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}
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else
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{
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d = context.Call(new _U64_U64(SoftFallback.ReverseBytes16_64), n);
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}
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SetAluDOrZR(context, d);
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}
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public static void Rev32(ArmEmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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if (op.RegisterSize == RegisterSize.Int32)
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{
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SetAluDOrZR(context, context.ByteSwap(n));
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}
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else
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{
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Operand d = context.Call(new _U64_U64(SoftFallback.ReverseBytes32_64), n);
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SetAluDOrZR(context, d);
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}
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}
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public static void Rev64(ArmEmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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SetAluDOrZR(context, context.ByteSwap(GetIntOrZR(context, op.Rn)));
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}
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public static void Rorv(ArmEmitterContext context)
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{
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SetAluDOrZR(context, context.RotateRight(GetAluN(context), GetAluMShift(context)));
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}
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private static Operand GetAluMShift(ArmEmitterContext context)
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{
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IOpCodeAluRs op = (IOpCodeAluRs)context.CurrOp;
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Operand m = GetIntOrZR(context, op.Rm);
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if (op.RegisterSize == RegisterSize.Int64)
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{
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m = context.ConvertI64ToI32(m);
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}
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return context.BitwiseAnd(m, Const(context.CurrOp.GetBitsCount() - 1));
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}
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private static void EmitCVFlagsClear(ArmEmitterContext context)
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{
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SetFlag(context, PState.CFlag, Const(0));
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SetFlag(context, PState.VFlag, Const(0));
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}
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public static void SetAluD(ArmEmitterContext context, Operand d)
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{
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SetAluD(context, d, x31IsZR: false);
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}
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public static void SetAluDOrZR(ArmEmitterContext context, Operand d)
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{
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SetAluD(context, d, x31IsZR: true);
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}
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public static void SetAluD(ArmEmitterContext context, Operand d, bool x31IsZR)
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{
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IOpCodeAlu op = (IOpCodeAlu)context.CurrOp;
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if ((x31IsZR || op is IOpCodeAluRs) && op.Rd == RegisterConsts.ZeroIndex)
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{
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return;
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}
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SetIntOrSP(context, op.Rd, d);
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}
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}
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}
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