mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-19 15:18:43 +02:00
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
352 lines
11 KiB
C#
352 lines
11 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitAluHelper
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{
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public static void EmitNZFlagsCheck(ArmEmitterContext context, Operand d)
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{
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SetFlag(context, PState.NFlag, context.ICompareLess (d, Const(d.Type, 0)));
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SetFlag(context, PState.ZFlag, context.ICompareEqual(d, Const(d.Type, 0)));
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}
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public static void EmitAdcsCCheck(ArmEmitterContext context, Operand n, Operand d)
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{
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// C = (Rd == Rn && CIn) || Rd < Rn
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Operand cIn = GetFlag(PState.CFlag);
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Operand cOut = context.BitwiseAnd(context.ICompareEqual(d, n), cIn);
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cOut = context.BitwiseOr(cOut, context.ICompareLessUI(d, n));
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SetFlag(context, PState.CFlag, cOut);
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}
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public static void EmitAddsCCheck(ArmEmitterContext context, Operand n, Operand d)
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{
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// C = Rd < Rn
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SetFlag(context, PState.CFlag, context.ICompareLessUI(d, n));
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}
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public static void EmitAddsVCheck(ArmEmitterContext context, Operand n, Operand m, Operand d)
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{
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// V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0
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Operand vOut = context.BitwiseExclusiveOr(d, n);
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vOut = context.BitwiseAnd(vOut, context.BitwiseNot(context.BitwiseExclusiveOr(n, m)));
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vOut = context.ICompareLess(vOut, Const(vOut.Type, 0));
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SetFlag(context, PState.VFlag, vOut);
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}
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public static void EmitSbcsCCheck(ArmEmitterContext context, Operand n, Operand m)
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{
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// C = (Rn == Rm && CIn) || Rn > Rm
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Operand cIn = GetFlag(PState.CFlag);
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Operand cOut = context.BitwiseAnd(context.ICompareEqual(n, m), cIn);
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cOut = context.BitwiseOr(cOut, context.ICompareGreaterUI(n, m));
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SetFlag(context, PState.CFlag, cOut);
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}
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public static void EmitSubsCCheck(ArmEmitterContext context, Operand n, Operand m)
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{
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// C = Rn >= Rm
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SetFlag(context, PState.CFlag, context.ICompareGreaterOrEqualUI(n, m));
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}
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public static void EmitSubsVCheck(ArmEmitterContext context, Operand n, Operand m, Operand d)
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{
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// V = (Rd ^ Rn) & (Rn ^ Rm) < 0
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Operand vOut = context.BitwiseExclusiveOr(d, n);
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vOut = context.BitwiseAnd(vOut, context.BitwiseExclusiveOr(n, m));
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vOut = context.ICompareLess(vOut, Const(vOut.Type, 0));
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SetFlag(context, PState.VFlag, vOut);
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}
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public static Operand GetAluN(ArmEmitterContext context)
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{
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if (context.CurrOp is IOpCodeAlu op)
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{
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if (op.DataOp == DataOp.Logical || op is IOpCodeAluRs)
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{
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return GetIntOrZR(context, op.Rn);
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}
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else
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{
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return GetIntOrSP(context, op.Rn);
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}
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}
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else if (context.CurrOp is IOpCode32Alu op32)
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{
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return GetIntA32(context, op32.Rn);
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}
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else
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{
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throw InvalidOpCodeType(context.CurrOp);
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}
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}
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public static Operand GetAluM(ArmEmitterContext context, bool setCarry = true)
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{
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switch (context.CurrOp)
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{
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// ARM32.
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case OpCode32AluImm op:
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{
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if (op.SetFlags && op.IsRotated)
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{
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SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31));
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}
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return Const(op.Immediate);
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}
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case OpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
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case OpCodeT16AluImm8 op: return Const(op.Immediate);
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// ARM64.
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case IOpCodeAluImm op:
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{
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if (op.GetOperandType() == OperandType.I32)
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{
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return Const((int)op.Immediate);
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}
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else
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{
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return Const(op.Immediate);
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}
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}
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case IOpCodeAluRs op:
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{
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Operand value = GetIntOrZR(context, op.Rm);
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switch (op.ShiftType)
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{
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case ShiftType.Lsl: value = context.ShiftLeft (value, Const(op.Shift)); break;
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case ShiftType.Lsr: value = context.ShiftRightUI(value, Const(op.Shift)); break;
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case ShiftType.Asr: value = context.ShiftRightSI(value, Const(op.Shift)); break;
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case ShiftType.Ror: value = context.RotateRight (value, Const(op.Shift)); break;
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}
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return value;
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}
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case IOpCodeAluRx op:
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{
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Operand value = GetExtendedM(context, op.Rm, op.IntType);
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value = context.ShiftLeft(value, Const(op.Shift));
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return value;
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}
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default: throw InvalidOpCodeType(context.CurrOp);
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}
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}
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private static Exception InvalidOpCodeType(OpCode opCode)
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{
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return new InvalidOperationException($"Invalid OpCode type \"{opCode?.GetType().Name ?? "null"}\".");
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}
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// ARM32 helpers.
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private static Operand GetMShiftedByImmediate(ArmEmitterContext context, OpCode32AluRsImm op, bool setCarry)
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{
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Operand m = GetIntA32(context, op.Rm);
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int shift = op.Imm;
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if (shift == 0)
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{
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switch (op.ShiftType)
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{
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case ShiftType.Lsr: shift = 32; break;
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case ShiftType.Asr: shift = 32; break;
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case ShiftType.Ror: shift = 1; break;
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}
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}
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if (shift != 0)
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{
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setCarry &= op.SetFlags;
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switch (op.ShiftType)
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{
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case ShiftType.Lsl: m = GetLslC(context, m, setCarry, shift); break;
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case ShiftType.Lsr: m = GetLsrC(context, m, setCarry, shift); break;
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case ShiftType.Asr: m = GetAsrC(context, m, setCarry, shift); break;
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case ShiftType.Ror:
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if (op.Imm != 0)
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{
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m = GetRorC(context, m, setCarry, shift);
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}
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else
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{
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m = GetRrxC(context, m, setCarry);
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}
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break;
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}
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}
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return m;
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}
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private static Operand GetLslC(ArmEmitterContext context, Operand m, bool setCarry, int shift)
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{
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if ((uint)shift > 32)
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{
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return GetShiftByMoreThan32(context, setCarry);
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}
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else if (shift == 32)
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{
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if (setCarry)
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{
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SetCarryMLsb(context, m);
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}
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return Const(0);
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}
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else
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{
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if (setCarry)
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{
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Operand cOut = context.ShiftRightUI(m, Const(32 - shift));
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cOut = context.BitwiseAnd(cOut, Const(1));
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SetFlag(context, PState.CFlag, cOut);
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}
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return context.ShiftLeft(m, Const(shift));
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}
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}
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private static Operand GetLsrC(ArmEmitterContext context, Operand m, bool setCarry, int shift)
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{
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if ((uint)shift > 32)
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{
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return GetShiftByMoreThan32(context, setCarry);
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}
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else if (shift == 32)
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{
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if (setCarry)
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{
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SetCarryMMsb(context, m);
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}
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return Const(0);
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}
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else
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{
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if (setCarry)
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{
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SetCarryMShrOut(context, m, shift);
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}
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return context.ShiftRightUI(m, Const(shift));
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}
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}
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private static Operand GetShiftByMoreThan32(ArmEmitterContext context, bool setCarry)
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{
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if (setCarry)
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{
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SetFlag(context, PState.CFlag, Const(0));;
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}
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return Const(0);
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}
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private static Operand GetAsrC(ArmEmitterContext context, Operand m, bool setCarry, int shift)
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{
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if ((uint)shift >= 32)
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{
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m = context.ShiftRightSI(m, Const(31));
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if (setCarry)
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{
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SetCarryMLsb(context, m);
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}
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return m;
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}
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else
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{
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if (setCarry)
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{
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SetCarryMShrOut(context, m, shift);
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}
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return context.ShiftRightSI(m, Const(shift));
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}
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}
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private static Operand GetRorC(ArmEmitterContext context, Operand m, bool setCarry, int shift)
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{
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shift &= 0x1f;
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m = context.RotateRight(m, Const(shift));
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if (setCarry)
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{
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SetCarryMMsb(context, m);
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}
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return m;
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}
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private static Operand GetRrxC(ArmEmitterContext context, Operand m, bool setCarry)
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{
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// Rotate right by 1 with carry.
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Operand cIn = context.Copy(GetFlag(PState.CFlag));
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if (setCarry)
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{
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SetCarryMLsb(context, m);
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}
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m = context.ShiftRightUI(m, Const(1));
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m = context.BitwiseOr(m, context.ShiftLeft(cIn, Const(31)));
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return m;
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}
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private static void SetCarryMLsb(ArmEmitterContext context, Operand m)
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{
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SetFlag(context, PState.CFlag, context.BitwiseAnd(m, Const(1)));
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}
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private static void SetCarryMMsb(ArmEmitterContext context, Operand m)
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{
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SetFlag(context, PState.CFlag, context.ShiftRightUI(m, Const(31)));
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}
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private static void SetCarryMShrOut(ArmEmitterContext context, Operand m, int shift)
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{
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Operand cOut = context.ShiftRightUI(m, Const(shift - 1));
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cOut = context.BitwiseAnd(cOut, Const(1));
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SetFlag(context, PState.CFlag, cOut);
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}
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}
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}
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