mirror of
https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
261 lines
10 KiB
C#
261 lines
10 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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[Flags]
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private enum AccessType
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{
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None = 0,
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Ordered = 1,
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Exclusive = 2,
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OrderedEx = Ordered | Exclusive
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}
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public static void Clrex(ArmEmitterContext context)
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{
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context.Call(new _Void(NativeInterface.ClearExclusive));
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}
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public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Dsb(ArmEmitterContext context) => EmitBarrier(context);
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public static void Ldar(ArmEmitterContext context) => EmitLdr(context, AccessType.Ordered);
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public static void Ldaxr(ArmEmitterContext context) => EmitLdr(context, AccessType.OrderedEx);
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public static void Ldxr(ArmEmitterContext context) => EmitLdr(context, AccessType.Exclusive);
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public static void Ldxp(ArmEmitterContext context) => EmitLdp(context, AccessType.Exclusive);
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public static void Ldaxp(ArmEmitterContext context) => EmitLdp(context, AccessType.OrderedEx);
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private static void EmitLdr(ArmEmitterContext context, AccessType accType)
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{
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EmitLoadEx(context, accType, pair: false);
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}
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private static void EmitLdp(ArmEmitterContext context, AccessType accType)
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{
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EmitLoadEx(context, accType, pair: true);
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}
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private static void EmitLoadEx(ArmEmitterContext context, AccessType accType, bool pair)
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{
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OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
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bool ordered = (accType & AccessType.Ordered) != 0;
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bool exclusive = (accType & AccessType.Exclusive) != 0;
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if (ordered)
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{
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EmitBarrier(context);
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}
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Operand address = context.Copy(GetIntOrSP(context, op.Rn));
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if (pair)
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{
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// Exclusive loads should be atomic. For pairwise loads, we need to
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// read all the data at once. For a 32-bits pairwise load, we do a
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// simple 64-bits load, for a 128-bits load, we need to call a special
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// method to read 128-bits atomically.
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if (op.Size == 2)
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{
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Operand value = EmitLoad(context, address, exclusive, 3);
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Operand valueLow = context.ConvertI64ToI32(value);
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valueLow = context.ZeroExtend32(OperandType.I64, valueLow);
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Operand valueHigh = context.ShiftRightUI(value, Const(32));
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SetIntOrZR(context, op.Rt, valueLow);
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SetIntOrZR(context, op.Rt2, valueHigh);
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}
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else if (op.Size == 3)
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{
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Operand value = EmitLoad(context, address, exclusive, 4);
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Operand valueLow = context.VectorExtract(OperandType.I64, value, 0);
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Operand valueHigh = context.VectorExtract(OperandType.I64, value, 1);
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SetIntOrZR(context, op.Rt, valueLow);
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SetIntOrZR(context, op.Rt2, valueHigh);
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}
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else
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{
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throw new InvalidOperationException($"Invalid load size of {1 << op.Size} bytes.");
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}
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}
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else
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{
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// 8, 16, 32 or 64-bits (non-pairwise) load.
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Operand value = EmitLoad(context, address, exclusive, op.Size);
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SetIntOrZR(context, op.Rt, value);
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}
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}
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private static Operand EmitLoad(
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ArmEmitterContext context,
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Operand address,
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bool exclusive,
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int size)
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{
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Delegate fallbackMethodDlg = null;
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if (exclusive)
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{
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switch (size)
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{
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case 0: fallbackMethodDlg = new _U8_U64 (NativeInterface.ReadByteExclusive); break;
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case 1: fallbackMethodDlg = new _U16_U64 (NativeInterface.ReadUInt16Exclusive); break;
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case 2: fallbackMethodDlg = new _U32_U64 (NativeInterface.ReadUInt32Exclusive); break;
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case 3: fallbackMethodDlg = new _U64_U64 (NativeInterface.ReadUInt64Exclusive); break;
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case 4: fallbackMethodDlg = new _V128_U64(NativeInterface.ReadVector128Exclusive); break;
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}
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}
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else
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{
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switch (size)
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{
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case 0: fallbackMethodDlg = new _U8_U64 (NativeInterface.ReadByte); break;
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case 1: fallbackMethodDlg = new _U16_U64 (NativeInterface.ReadUInt16); break;
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case 2: fallbackMethodDlg = new _U32_U64 (NativeInterface.ReadUInt32); break;
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case 3: fallbackMethodDlg = new _U64_U64 (NativeInterface.ReadUInt64); break;
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case 4: fallbackMethodDlg = new _V128_U64(NativeInterface.ReadVector128); break;
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}
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}
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return context.Call(fallbackMethodDlg, address);
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}
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public static void Pfrm(ArmEmitterContext context)
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{
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// Memory Prefetch, execute as no-op.
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}
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public static void Stlr(ArmEmitterContext context) => EmitStr(context, AccessType.Ordered);
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public static void Stlxr(ArmEmitterContext context) => EmitStr(context, AccessType.OrderedEx);
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public static void Stxr(ArmEmitterContext context) => EmitStr(context, AccessType.Exclusive);
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public static void Stxp(ArmEmitterContext context) => EmitStp(context, AccessType.Exclusive);
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public static void Stlxp(ArmEmitterContext context) => EmitStp(context, AccessType.OrderedEx);
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private static void EmitStr(ArmEmitterContext context, AccessType accType)
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{
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EmitStoreEx(context, accType, pair: false);
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}
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private static void EmitStp(ArmEmitterContext context, AccessType accType)
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{
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EmitStoreEx(context, accType, pair: true);
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}
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private static void EmitStoreEx(ArmEmitterContext context, AccessType accType, bool pair)
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{
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OpCodeMemEx op = (OpCodeMemEx)context.CurrOp;
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bool ordered = (accType & AccessType.Ordered) != 0;
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bool exclusive = (accType & AccessType.Exclusive) != 0;
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if (ordered)
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{
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EmitBarrier(context);
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}
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Operand address = context.Copy(GetIntOrSP(context, op.Rn));
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Operand t = GetIntOrZR(context, op.Rt);
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Operand s = null;
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if (pair)
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{
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Debug.Assert(op.Size == 2 || op.Size == 3, "Invalid size for pairwise store.");
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Operand t2 = GetIntOrZR(context, op.Rt2);
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Operand value;
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if (op.Size == 2)
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{
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value = context.BitwiseOr(t, context.ShiftLeft(t2, Const(32)));
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}
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else /* if (op.Size == 3) */
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{
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value = context.VectorInsert(context.VectorZero(), t, 0);
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value = context.VectorInsert(value, t2, 1);
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}
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s = EmitStore(context, address, value, exclusive, op.Size + 1);
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}
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else
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{
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s = EmitStore(context, address, t, exclusive, op.Size);
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}
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if (s != null)
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{
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// This is only needed for exclusive stores. The function returns 0
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// when the store is successful, and 1 otherwise.
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SetIntOrZR(context, op.Rs, s);
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}
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}
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private static Operand EmitStore(
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ArmEmitterContext context,
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Operand address,
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Operand value,
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bool exclusive,
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int size)
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{
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if (size < 3)
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{
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value = context.ConvertI64ToI32(value);
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}
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Delegate fallbackMethodDlg = null;
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if (exclusive)
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{
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switch (size)
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{
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case 0: fallbackMethodDlg = new _S32_U64_U8 (NativeInterface.WriteByteExclusive); break;
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case 1: fallbackMethodDlg = new _S32_U64_U16 (NativeInterface.WriteUInt16Exclusive); break;
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case 2: fallbackMethodDlg = new _S32_U64_U32 (NativeInterface.WriteUInt32Exclusive); break;
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case 3: fallbackMethodDlg = new _S32_U64_U64 (NativeInterface.WriteUInt64Exclusive); break;
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case 4: fallbackMethodDlg = new _S32_U64_V128(NativeInterface.WriteVector128Exclusive); break;
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}
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return context.Call(fallbackMethodDlg, address, value);
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}
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else
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{
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switch (size)
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{
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case 0: fallbackMethodDlg = new _Void_U64_U8 (NativeInterface.WriteByte); break;
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case 1: fallbackMethodDlg = new _Void_U64_U16 (NativeInterface.WriteUInt16); break;
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case 2: fallbackMethodDlg = new _Void_U64_U32 (NativeInterface.WriteUInt32); break;
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case 3: fallbackMethodDlg = new _Void_U64_U64 (NativeInterface.WriteUInt64); break;
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case 4: fallbackMethodDlg = new _Void_U64_V128(NativeInterface.WriteVector128); break;
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}
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context.Call(fallbackMethodDlg, address, value);
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return null;
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}
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}
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private static void EmitBarrier(ArmEmitterContext context)
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{
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// Note: This barrier is most likely not necessary, and probably
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// doesn't make any difference since we need to do a ton of stuff
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// (software MMU emulation) to read or write anything anyway.
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}
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}
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} |