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https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
413 lines
14 KiB
C#
413 lines
14 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using System;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Translation
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{
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static class RegisterUsage
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{
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private const long CallerSavedIntRegistersMask = 0x7fL << 9;
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private const long PStateNzcvFlagsMask = 0xfL << 60;
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private const long CallerSavedVecRegistersMask = 0xffffL << 16;
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private const int RegsCount = 32;
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private const int RegsMask = RegsCount - 1;
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private struct RegisterMask : IEquatable<RegisterMask>
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{
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public long IntMask { get; set; }
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public long VecMask { get; set; }
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public RegisterMask(long intMask, long vecMask)
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{
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IntMask = intMask;
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VecMask = vecMask;
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}
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public static RegisterMask operator &(RegisterMask x, RegisterMask y)
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{
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return new RegisterMask(x.IntMask & y.IntMask, x.VecMask & y.VecMask);
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}
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public static RegisterMask operator |(RegisterMask x, RegisterMask y)
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{
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return new RegisterMask(x.IntMask | y.IntMask, x.VecMask | y.VecMask);
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}
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public static RegisterMask operator ~(RegisterMask x)
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{
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return new RegisterMask(~x.IntMask, ~x.VecMask);
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}
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public static bool operator ==(RegisterMask x, RegisterMask y)
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{
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return x.Equals(y);
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}
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public static bool operator !=(RegisterMask x, RegisterMask y)
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{
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return !x.Equals(y);
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}
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public override bool Equals(object obj)
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{
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return obj is RegisterMask regMask && Equals(regMask);
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}
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public bool Equals(RegisterMask other)
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{
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return IntMask == other.IntMask && VecMask == other.VecMask;
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}
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public override int GetHashCode()
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{
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return HashCode.Combine(IntMask, VecMask);
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}
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}
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public static void RunPass(ControlFlowGraph cfg, bool isCompleteFunction)
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{
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// Compute local register inputs and outputs used inside blocks.
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RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] localOutputs = new RegisterMask[cfg.Blocks.Count];
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foreach (BasicBlock block in cfg.Blocks)
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{
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foreach (Node node in block.Operations)
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{
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Operation operation = node as Operation;
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for (int srcIndex = 0; srcIndex < operation.SourcesCount; srcIndex++)
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{
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Operand source = operation.GetSource(srcIndex);
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if (source.Kind != OperandKind.Register)
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{
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continue;
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}
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Register register = source.GetRegister();
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localInputs[block.Index] |= GetMask(register) & ~localOutputs[block.Index];
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}
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if (operation.Destination != null && operation.Destination.Kind == OperandKind.Register)
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{
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localOutputs[block.Index] |= GetMask(operation.Destination.GetRegister());
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}
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}
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}
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// Compute global register inputs and outputs used across blocks.
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RegisterMask[] globalCmnOutputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] globalOutputs = new RegisterMask[cfg.Blocks.Count];
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bool modified;
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bool firstPass = true;
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do
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{
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modified = false;
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// Compute register outputs.
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for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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if (block.Predecessors.Count != 0 && !HasContextLoad(block))
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{
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BasicBlock predecessor = block.Predecessors[0];
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RegisterMask cmnOutputs = localOutputs[predecessor.Index] | globalCmnOutputs[predecessor.Index];
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RegisterMask outputs = globalOutputs[predecessor.Index];
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for (int pIndex = 1; pIndex < block.Predecessors.Count; pIndex++)
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{
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predecessor = block.Predecessors[pIndex];
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cmnOutputs &= localOutputs[predecessor.Index] | globalCmnOutputs[predecessor.Index];
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outputs |= globalOutputs[predecessor.Index];
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}
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globalInputs[block.Index] |= outputs & ~cmnOutputs;
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if (!firstPass)
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{
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cmnOutputs &= globalCmnOutputs[block.Index];
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}
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if (Exchange(globalCmnOutputs, block.Index, cmnOutputs))
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{
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modified = true;
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}
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outputs |= localOutputs[block.Index];
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if (Exchange(globalOutputs, block.Index, globalOutputs[block.Index] | outputs))
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{
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modified = true;
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}
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}
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else if (Exchange(globalOutputs, block.Index, localOutputs[block.Index]))
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{
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modified = true;
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}
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}
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// Compute register inputs.
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for (int index = 0; index < cfg.PostOrderBlocks.Length; index++)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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RegisterMask inputs = localInputs[block.Index];
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if (block.Next != null)
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{
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inputs |= globalInputs[block.Next.Index];
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}
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if (block.Branch != null)
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{
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inputs |= globalInputs[block.Branch.Index];
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}
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inputs &= ~globalCmnOutputs[block.Index];
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if (Exchange(globalInputs, block.Index, globalInputs[block.Index] | inputs))
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{
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modified = true;
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}
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}
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firstPass = false;
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}
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while (modified);
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// Insert load and store context instructions where needed.
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foreach (BasicBlock block in cfg.Blocks)
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{
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bool hasContextLoad = HasContextLoad(block);
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if (hasContextLoad)
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{
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block.Operations.RemoveFirst();
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}
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// The only block without any predecessor should be the entry block.
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// It always needs a context load as it is the first block to run.
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if (block.Predecessors.Count == 0 || hasContextLoad)
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{
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LoadLocals(block, globalInputs[block.Index].VecMask, RegisterType.Vector);
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LoadLocals(block, globalInputs[block.Index].IntMask, RegisterType.Integer);
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}
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bool hasContextStore = HasContextStore(block);
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if (hasContextStore)
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{
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block.Operations.RemoveLast();
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}
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if (EndsWithReturn(block) || hasContextStore)
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{
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StoreLocals(block, globalOutputs[block.Index].IntMask, RegisterType.Integer, isCompleteFunction);
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StoreLocals(block, globalOutputs[block.Index].VecMask, RegisterType.Vector, isCompleteFunction);
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}
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}
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}
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private static bool HasContextLoad(BasicBlock block)
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{
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return StartsWith(block, Instruction.LoadFromContext) && block.Operations.First.Value.SourcesCount == 0;
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}
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private static bool HasContextStore(BasicBlock block)
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{
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return EndsWith(block, Instruction.StoreToContext) && block.GetLastOp().SourcesCount == 0;
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}
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private static bool StartsWith(BasicBlock block, Instruction inst)
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{
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if (block.Operations.Count == 0)
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{
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return false;
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}
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return block.Operations.First.Value is Operation operation && operation.Instruction == inst;
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}
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private static bool EndsWith(BasicBlock block, Instruction inst)
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{
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if (block.Operations.Count == 0)
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{
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return false;
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}
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return block.Operations.Last.Value is Operation operation && operation.Instruction == inst;
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}
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private static RegisterMask GetMask(Register register)
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{
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long intMask = 0;
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long vecMask = 0;
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switch (register.Type)
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{
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case RegisterType.Flag: intMask = (1L << RegsCount) << register.Index; break;
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case RegisterType.Integer: intMask = 1L << register.Index; break;
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case RegisterType.Vector: vecMask = 1L << register.Index; break;
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}
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return new RegisterMask(intMask, vecMask);
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}
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private static bool Exchange(RegisterMask[] masks, int blkIndex, RegisterMask value)
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{
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RegisterMask oldValue = masks[blkIndex];
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masks[blkIndex] = value;
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return oldValue != value;
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}
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private static void LoadLocals(BasicBlock block, long inputs, RegisterType baseType)
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{
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Operand arg0 = Local(OperandType.I64);
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for (int bit = 63; bit >= 0; bit--)
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{
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long mask = 1L << bit;
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if ((inputs & mask) == 0)
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{
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continue;
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}
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Operand dest = GetRegFromBit(bit, baseType);
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long offset = NativeContext.GetRegisterOffset(dest.GetRegister());
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Operand addr = Local(OperandType.I64);
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Operation loadOp = new Operation(Instruction.Load, dest, addr);
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block.Operations.AddFirst(loadOp);
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Operation calcOffsOp = new Operation(Instruction.Add, addr, arg0, Const(offset));
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block.Operations.AddFirst(calcOffsOp);
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}
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Operation loadArg0 = new Operation(Instruction.LoadArgument, arg0, Const(0));
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block.Operations.AddFirst(loadArg0);
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}
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private static void StoreLocals(BasicBlock block, long outputs, RegisterType baseType, bool isCompleteFunction)
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{
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if (Optimizations.AssumeStrictAbiCompliance && isCompleteFunction)
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{
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if (baseType == RegisterType.Integer || baseType == RegisterType.Flag)
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{
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outputs = ClearCallerSavedIntRegs(outputs);
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}
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else /* if (baseType == RegisterType.Vector) */
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{
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outputs = ClearCallerSavedVecRegs(outputs);
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}
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}
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Operand arg0 = Local(OperandType.I64);
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Operation loadArg0 = new Operation(Instruction.LoadArgument, arg0, Const(0));
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block.Append(loadArg0);
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for (int bit = 0; bit < 64; bit++)
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{
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long mask = 1L << bit;
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if ((outputs & mask) == 0)
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{
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continue;
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}
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Operand source = GetRegFromBit(bit, baseType);
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long offset = NativeContext.GetRegisterOffset(source.GetRegister());
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Operand addr = Local(OperandType.I64);
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Operation calcOffsOp = new Operation(Instruction.Add, addr, arg0, Const(offset));
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block.Append(calcOffsOp);
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Operation storeOp = new Operation(Instruction.Store, null, addr, source);
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block.Append(storeOp);
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}
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}
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private static Operand GetRegFromBit(int bit, RegisterType baseType)
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{
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if (bit < RegsCount)
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{
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return new Operand(bit, baseType, GetOperandType(baseType));
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}
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else if (baseType == RegisterType.Integer)
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{
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return new Operand(bit & RegsMask, RegisterType.Flag, OperandType.I32);
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(bit));
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}
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}
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private static OperandType GetOperandType(RegisterType type)
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{
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switch (type)
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{
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case RegisterType.Flag: return OperandType.I32;
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case RegisterType.Integer: return OperandType.I64;
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case RegisterType.Vector: return OperandType.V128;
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}
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throw new ArgumentException($"Invalid register type \"{type}\".");
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}
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private static bool EndsWithReturn(BasicBlock block)
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{
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if (!(block.GetLastOp() is Operation operation))
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{
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return false;
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}
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return operation.Instruction == Instruction.Return;
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}
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private static long ClearCallerSavedIntRegs(long mask)
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{
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// TODO: ARM32 support.
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mask &= ~(CallerSavedIntRegistersMask | PStateNzcvFlagsMask);
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return mask;
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}
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private static long ClearCallerSavedVecRegs(long mask)
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{
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// TODO: ARM32 support.
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mask &= ~CallerSavedVecRegistersMask;
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return mask;
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}
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}
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} |