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https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
293 lines
9.1 KiB
C#
293 lines
9.1 KiB
C#
using ARMeilleure.Common;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using System.Collections.Generic;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Translation
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{
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static partial class Ssa
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{
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private class DefMap
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{
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private Dictionary<Register, Operand> _map;
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private BitMap _phiMasks;
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public DefMap()
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{
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_map = new Dictionary<Register, Operand>();
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_phiMasks = new BitMap(RegisterConsts.TotalCount);
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}
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public bool TryAddOperand(Register reg, Operand operand)
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{
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return _map.TryAdd(reg, operand);
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}
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public bool TryGetOperand(Register reg, out Operand operand)
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{
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return _map.TryGetValue(reg, out operand);
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}
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public bool AddPhi(Register reg)
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{
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return _phiMasks.Set(GetIdFromRegister(reg));
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}
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public bool HasPhi(Register reg)
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{
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return _phiMasks.IsSet(GetIdFromRegister(reg));
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}
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}
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public static void Construct(ControlFlowGraph cfg)
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{
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DefMap[] globalDefs = new DefMap[cfg.Blocks.Count];
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foreach (BasicBlock block in cfg.Blocks)
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{
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globalDefs[block.Index] = new DefMap();
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}
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Queue<BasicBlock> dfPhiBlocks = new Queue<BasicBlock>();
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// First pass, get all defs and locals uses.
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foreach (BasicBlock block in cfg.Blocks)
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{
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Operand[] localDefs = new Operand[RegisterConsts.TotalCount];
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LinkedListNode<Node> node = block.Operations.First;
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Operand RenameLocal(Operand operand)
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{
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if (operand != null && operand.Kind == OperandKind.Register)
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{
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Operand local = localDefs[GetIdFromRegister(operand.GetRegister())];
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operand = local ?? operand;
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}
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return operand;
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}
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while (node != null)
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{
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if (node.Value is Operation operation)
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{
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for (int index = 0; index < operation.SourcesCount; index++)
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{
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operation.SetSource(index, RenameLocal(operation.GetSource(index)));
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}
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Operand dest = operation.Destination;
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if (dest != null && dest.Kind == OperandKind.Register)
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{
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Operand local = Local(dest.Type);
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localDefs[GetIdFromRegister(dest.GetRegister())] = local;
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operation.Destination = local;
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}
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}
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node = node.Next;
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}
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for (int index = 0; index < RegisterConsts.TotalCount; index++)
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{
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Operand local = localDefs[index];
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if (local == null)
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{
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continue;
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}
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Register reg = GetRegisterFromId(index);
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globalDefs[block.Index].TryAddOperand(reg, local);
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dfPhiBlocks.Enqueue(block);
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while (dfPhiBlocks.TryDequeue(out BasicBlock dfPhiBlock))
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{
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foreach (BasicBlock domFrontier in dfPhiBlock.DominanceFrontiers)
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{
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if (globalDefs[domFrontier.Index].AddPhi(reg))
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{
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dfPhiBlocks.Enqueue(domFrontier);
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}
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}
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}
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}
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}
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// Second pass, rename variables with definitions on different blocks.
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foreach (BasicBlock block in cfg.Blocks)
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{
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Operand[] localDefs = new Operand[RegisterConsts.TotalCount];
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LinkedListNode<Node> node = block.Operations.First;
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Operand RenameGlobal(Operand operand)
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{
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if (operand != null && operand.Kind == OperandKind.Register)
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{
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int key = GetIdFromRegister(operand.GetRegister());
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Operand local = localDefs[key];
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if (local == null)
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{
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local = FindDef(globalDefs, block, operand);
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localDefs[key] = local;
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}
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operand = local;
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}
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return operand;
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}
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while (node != null)
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{
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if (node.Value is Operation operation)
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{
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for (int index = 0; index < operation.SourcesCount; index++)
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{
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operation.SetSource(index, RenameGlobal(operation.GetSource(index)));
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}
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}
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node = node.Next;
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}
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}
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}
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private static Operand FindDef(DefMap[] globalDefs, BasicBlock current, Operand operand)
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{
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if (globalDefs[current.Index].HasPhi(operand.GetRegister()))
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{
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return InsertPhi(globalDefs, current, operand);
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}
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if (current != current.ImmediateDominator)
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{
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return FindDefOnPred(globalDefs, current.ImmediateDominator, operand);
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}
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return Undef();
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}
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private static Operand FindDefOnPred(DefMap[] globalDefs, BasicBlock current, Operand operand)
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{
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BasicBlock previous;
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do
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{
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DefMap defMap = globalDefs[current.Index];
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Register reg = operand.GetRegister();
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if (defMap.TryGetOperand(reg, out Operand lastDef))
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{
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return lastDef;
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}
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if (defMap.HasPhi(reg))
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{
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return InsertPhi(globalDefs, current, operand);
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}
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previous = current;
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current = current.ImmediateDominator;
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}
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while (previous != current);
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return Undef();
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}
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private static Operand InsertPhi(DefMap[] globalDefs, BasicBlock block, Operand operand)
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{
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// This block has a Phi that has not been materialized yet, but that
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// would define a new version of the variable we're looking for. We need
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// to materialize the Phi, add all the block/operand pairs into the Phi, and
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// then use the definition from that Phi.
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Operand local = Local(operand.Type);
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PhiNode phi = new PhiNode(local, block.Predecessors.Count);
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AddPhi(block, phi);
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globalDefs[block.Index].TryAddOperand(operand.GetRegister(), local);
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for (int index = 0; index < block.Predecessors.Count; index++)
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{
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BasicBlock predecessor = block.Predecessors[index];
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phi.SetBlock(index, predecessor);
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phi.SetSource(index, FindDefOnPred(globalDefs, predecessor, operand));
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}
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return local;
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}
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private static void AddPhi(BasicBlock block, PhiNode phi)
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{
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LinkedListNode<Node> node = block.Operations.First;
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if (node != null)
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{
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while (node.Next?.Value is PhiNode)
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{
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node = node.Next;
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}
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}
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if (node?.Value is PhiNode)
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{
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block.Operations.AddAfter(node, phi);
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}
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else
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{
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block.Operations.AddFirst(phi);
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}
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}
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private static int GetIdFromRegister(Register reg)
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{
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if (reg.Type == RegisterType.Integer)
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{
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return reg.Index;
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}
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else if (reg.Type == RegisterType.Vector)
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{
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return RegisterConsts.IntRegsCount + reg.Index;
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}
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else /* if (reg.Type == RegisterType.Flag) */
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{
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return RegisterConsts.IntAndVecRegsCount + reg.Index;
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}
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}
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private static Register GetRegisterFromId(int id)
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{
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if (id < RegisterConsts.IntRegsCount)
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{
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return new Register(id, RegisterType.Integer);
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}
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else if (id < RegisterConsts.IntAndVecRegsCount)
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{
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return new Register(id - RegisterConsts.IntRegsCount, RegisterType.Vector);
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}
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else /* if (id < RegisterConsts.TotalCount) */
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{
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return new Register(id - RegisterConsts.IntAndVecRegsCount, RegisterType.Flag);
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}
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}
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}
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} |