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https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
253 lines
No EOL
8 KiB
C#
253 lines
No EOL
8 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.Diagnostics;
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using ARMeilleure.Instructions;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Memory;
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using ARMeilleure.State;
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using System;
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using System.Collections.Concurrent;
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using System.Threading;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Translation
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{
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public class Translator : ITranslator
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{
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private const ulong CallFlag = InstEmitFlowHelper.CallFlag;
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private MemoryManager _memory;
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private ConcurrentDictionary<ulong, TranslatedFunction> _funcs;
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private PriorityQueue<ulong> _backgroundQueue;
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private AutoResetEvent _backgroundTranslatorEvent;
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private volatile int _threadCount;
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public Translator(MemoryManager memory)
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{
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_memory = memory;
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_funcs = new ConcurrentDictionary<ulong, TranslatedFunction>();
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_backgroundQueue = new PriorityQueue<ulong>(2);
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_backgroundTranslatorEvent = new AutoResetEvent(false);
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}
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private void TranslateQueuedSubs()
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{
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while (_threadCount != 0)
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{
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if (_backgroundQueue.TryDequeue(out ulong address))
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{
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TranslatedFunction func = Translate(address, ExecutionMode.Aarch64, highCq: true);
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_funcs.AddOrUpdate(address, func, (key, oldFunc) => func);
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}
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else
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{
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_backgroundTranslatorEvent.WaitOne();
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}
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}
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}
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public void Execute(IExecutionContext ctx, ulong address)
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{
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State.ExecutionContext context = (State.ExecutionContext)ctx;
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if (Interlocked.Increment(ref _threadCount) == 1)
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{
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Thread backgroundTranslatorThread = new Thread(TranslateQueuedSubs);
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backgroundTranslatorThread.Priority = ThreadPriority.Lowest;
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backgroundTranslatorThread.Start();
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}
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Statistics.InitializeTimer();
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NativeInterface.RegisterThread(context, _memory);
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do
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{
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address = ExecuteSingle(context, address);
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}
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while (context.Running && (address & ~1UL) != 0);
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NativeInterface.UnregisterThread();
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if (Interlocked.Decrement(ref _threadCount) == 0)
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{
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_backgroundTranslatorEvent.Set();
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}
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}
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public ulong ExecuteSingle(State.ExecutionContext context, ulong address)
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{
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TranslatedFunction func = GetOrTranslate(address, context.ExecutionMode);
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Statistics.StartTimer();
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ulong nextAddr = func.Execute(context);
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Statistics.StopTimer(address);
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return nextAddr;
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}
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private TranslatedFunction GetOrTranslate(ulong address, ExecutionMode mode)
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{
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// TODO: Investigate how we should handle code at unaligned addresses.
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// Currently, those low bits are used to store special flags.
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bool isCallTarget = (address & CallFlag) != 0;
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address &= ~CallFlag;
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if (!_funcs.TryGetValue(address, out TranslatedFunction func))
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{
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func = Translate(address, mode, highCq: false);
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_funcs.TryAdd(address, func);
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}
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else if (isCallTarget && func.ShouldRejit())
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{
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_backgroundQueue.Enqueue(0, address);
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_backgroundTranslatorEvent.Set();
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}
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return func;
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}
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private TranslatedFunction Translate(ulong address, ExecutionMode mode, bool highCq)
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{
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ArmEmitterContext context = new ArmEmitterContext(_memory, Aarch32Mode.User);
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Logger.StartPass(PassName.Decoding);
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Block[] blocks = highCq
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? Decoder.DecodeFunction (_memory, address, mode)
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: Decoder.DecodeBasicBlock(_memory, address, mode);
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Logger.EndPass(PassName.Decoding);
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Logger.StartPass(PassName.Translation);
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EmitSynchronization(context);
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if (blocks[0].Address != address)
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{
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context.Branch(context.GetLabel(address));
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}
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ControlFlowGraph cfg = EmitAndGetCFG(context, blocks);
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Logger.EndPass(PassName.Translation);
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Logger.StartPass(PassName.RegisterUsage);
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RegisterUsage.RunPass(cfg, isCompleteFunction: false);
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Logger.EndPass(PassName.RegisterUsage);
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OperandType[] argTypes = new OperandType[] { OperandType.I64 };
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CompilerOptions options = highCq
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? CompilerOptions.HighCq
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: CompilerOptions.None;
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GuestFunction func = Compiler.Compile<GuestFunction>(cfg, argTypes, OperandType.I64, options);
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return new TranslatedFunction(func, rejit: !highCq);
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}
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private static ControlFlowGraph EmitAndGetCFG(ArmEmitterContext context, Block[] blocks)
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{
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for (int blkIndex = 0; blkIndex < blocks.Length; blkIndex++)
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{
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Block block = blocks[blkIndex];
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context.CurrBlock = block;
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context.MarkLabel(context.GetLabel(block.Address));
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for (int opcIndex = 0; opcIndex < block.OpCodes.Count; opcIndex++)
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{
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OpCode opCode = block.OpCodes[opcIndex];
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context.CurrOp = opCode;
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bool isLastOp = opcIndex == block.OpCodes.Count - 1;
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if (isLastOp && block.Branch != null && block.Branch.Address <= block.Address)
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{
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EmitSynchronization(context);
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}
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Operand lblPredicateSkip = null;
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if (opCode is OpCode32 op && op.Cond < Condition.Al)
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{
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lblPredicateSkip = Label();
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InstEmitFlowHelper.EmitCondBranch(context, lblPredicateSkip, op.Cond.Invert());
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}
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if (opCode.Instruction.Emitter != null)
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{
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opCode.Instruction.Emitter(context);
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}
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else
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{
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throw new InvalidOperationException($"Invalid instruction \"{opCode.Instruction.Name}\".");
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}
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if (lblPredicateSkip != null)
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{
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context.MarkLabel(lblPredicateSkip);
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// If this is the last op on the block, and there's no "next" block
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// after this one, then we have to return right now, with the address
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// of the next instruction to be executed (in the case that the condition
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// is false, and the branch was not taken, as all basic blocks should end
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// with some kind of branch).
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if (isLastOp && block.Next == null)
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{
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context.Return(Const(opCode.Address + (ulong)opCode.OpCodeSizeInBytes));
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}
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}
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}
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}
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return context.GetControlFlowGraph();
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}
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private static void EmitSynchronization(EmitterContext context)
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{
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long countOffs = NativeContext.GetCounterOffset();
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Operand countAddr = context.Add(context.LoadArgument(OperandType.I64, 0), Const(countOffs));
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Operand count = context.Load(OperandType.I32, countAddr);
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Operand lblNonZero = Label();
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Operand lblExit = Label();
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context.BranchIfTrue(lblNonZero, count);
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context.Call(new _Void(NativeInterface.CheckSynchronization));
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context.Branch(lblExit);
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context.MarkLabel(lblNonZero);
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count = context.Subtract(count, Const(1));
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context.Store(countAddr, count);
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context.MarkLabel(lblExit);
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}
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}
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} |