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* Refactoring and optimization on CPU translation * Remove now unused property * Rename ilBlock -> block (local) * Change equality comparison on RegisterMask for consistency Co-Authored-By: gdkchan <gab.dark.100@gmail.com> * Add back the aggressive inlining attribute to the Synchronize method * Implement IEquatable on the Register struct * Fix identation
59 lines
No EOL
1.7 KiB
C#
59 lines
No EOL
1.7 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.IntermediateRepresentation;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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private enum CselOperation
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{
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None,
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Increment,
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Invert,
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Negate
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}
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public static void Csel(ILEmitterCtx context) => EmitCsel(context, CselOperation.None);
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public static void Csinc(ILEmitterCtx context) => EmitCsel(context, CselOperation.Increment);
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public static void Csinv(ILEmitterCtx context) => EmitCsel(context, CselOperation.Invert);
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public static void Csneg(ILEmitterCtx context) => EmitCsel(context, CselOperation.Negate);
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private static void EmitCsel(ILEmitterCtx context, CselOperation cselOp)
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{
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OpCodeCsel64 op = (OpCodeCsel64)context.CurrOp;
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ILLabel lblTrue = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.EmitCondBranch(lblTrue, op.Cond);
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context.EmitLdintzr(op.Rm);
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if (cselOp == CselOperation.Increment)
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{
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context.EmitLdc_I(1);
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context.Emit(OpCodes.Add);
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}
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else if (cselOp == CselOperation.Invert)
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{
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context.Emit(OpCodes.Not);
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}
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else if (cselOp == CselOperation.Negate)
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{
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context.Emit(OpCodes.Neg);
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}
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context.Emit(OpCodes.Br_S, lblEnd);
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context.MarkLabel(lblTrue);
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context.EmitLdintzr(op.Rn);
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context.MarkLabel(lblEnd);
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context.EmitStintzr(op.Rd);
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}
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}
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} |