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https://github.com/Ryujinx/Ryujinx.git
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* Fix typos * Remove unneeded using statements * Enforce var style more * Remove redundant qualifiers * Fix some indentation * Disable naming warnings on files with external enum names * Fix build * Mass find & replace for comments with no spacing * Standardize todo capitalization and for/if spacing
241 lines
No EOL
6 KiB
C#
241 lines
No EOL
6 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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using static ChocolArm64.Instructions.InstEmitMemoryHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void Adr(ILEmitterCtx context)
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{
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OpCodeAdr64 op = (OpCodeAdr64)context.CurrOp;
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context.EmitLdc_I(op.Position + op.Imm);
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context.EmitStintzr(op.Rd);
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}
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public static void Adrp(ILEmitterCtx context)
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{
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OpCodeAdr64 op = (OpCodeAdr64)context.CurrOp;
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context.EmitLdc_I((op.Position & ~0xfffL) + (op.Imm << 12));
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context.EmitStintzr(op.Rd);
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}
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public static void Ldr(ILEmitterCtx context) => EmitLdr(context, false);
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public static void Ldrs(ILEmitterCtx context) => EmitLdr(context, true);
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private static void EmitLdr(ILEmitterCtx context, bool signed)
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{
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OpCodeMem64 op = (OpCodeMem64)context.CurrOp;
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EmitLoadAddress(context);
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if (signed && op.Extend64)
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{
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EmitReadSx64Call(context, op.Size);
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}
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else if (signed)
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{
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EmitReadSx32Call(context, op.Size);
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}
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else
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{
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EmitReadZxCall(context, op.Size);
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}
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if (op is IOpCodeSimd64)
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{
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context.EmitStvec(op.Rt);
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}
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else
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{
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context.EmitStintzr(op.Rt);
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}
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EmitWBackIfNeeded(context);
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}
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public static void Ldr_Literal(ILEmitterCtx context)
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{
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IOpCodeLit64 op = (IOpCodeLit64)context.CurrOp;
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if (op.Prefetch)
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{
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return;
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}
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context.EmitLdc_I8(op.Imm);
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if (op.Signed)
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{
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EmitReadSx64Call(context, op.Size);
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}
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else
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{
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EmitReadZxCall(context, op.Size);
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}
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if (op is IOpCodeSimd64)
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{
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context.EmitStvec(op.Rt);
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}
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else
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{
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context.EmitStint(op.Rt);
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}
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}
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public static void Ldp(ILEmitterCtx context)
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{
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OpCodeMemPair64 op = (OpCodeMemPair64)context.CurrOp;
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void EmitReadAndStore(int rt)
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{
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if (op.Extend64)
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{
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EmitReadSx64Call(context, op.Size);
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}
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else
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{
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EmitReadZxCall(context, op.Size);
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}
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if (op is IOpCodeSimd64)
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{
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context.EmitStvec(rt);
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}
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else
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{
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context.EmitStintzr(rt);
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}
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}
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EmitLoadAddress(context);
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EmitReadAndStore(op.Rt);
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context.EmitLdtmp();
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context.EmitLdc_I8(1 << op.Size);
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context.Emit(OpCodes.Add);
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EmitReadAndStore(op.Rt2);
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EmitWBackIfNeeded(context);
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}
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public static void Str(ILEmitterCtx context)
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{
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OpCodeMem64 op = (OpCodeMem64)context.CurrOp;
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EmitLoadAddress(context);
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if (op is IOpCodeSimd64)
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{
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context.EmitLdvec(op.Rt);
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}
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else
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{
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context.EmitLdintzr(op.Rt);
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}
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EmitWriteCall(context, op.Size);
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EmitWBackIfNeeded(context);
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}
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public static void Stp(ILEmitterCtx context)
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{
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OpCodeMemPair64 op = (OpCodeMemPair64)context.CurrOp;
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EmitLoadAddress(context);
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if (op is IOpCodeSimd64)
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{
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context.EmitLdvec(op.Rt);
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}
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else
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{
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context.EmitLdintzr(op.Rt);
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}
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EmitWriteCall(context, op.Size);
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context.EmitLdtmp();
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context.EmitLdc_I8(1 << op.Size);
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context.Emit(OpCodes.Add);
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if (op is IOpCodeSimd64)
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{
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context.EmitLdvec(op.Rt2);
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}
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else
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{
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context.EmitLdintzr(op.Rt2);
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}
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EmitWriteCall(context, op.Size);
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EmitWBackIfNeeded(context);
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}
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private static void EmitLoadAddress(ILEmitterCtx context)
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{
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switch (context.CurrOp)
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{
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case OpCodeMemImm64 op:
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context.EmitLdint(op.Rn);
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if (!op.PostIdx)
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{
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// Pre-indexing.
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context.EmitLdc_I(op.Imm);
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context.Emit(OpCodes.Add);
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}
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break;
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case OpCodeMemReg64 op:
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context.EmitLdint(op.Rn);
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context.EmitLdintzr(op.Rm);
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context.EmitCast(op.IntType);
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if (op.Shift)
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{
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context.EmitLsl(op.Size);
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}
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context.Emit(OpCodes.Add);
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break;
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}
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// Save address to Scratch var since the register value may change.
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context.Emit(OpCodes.Dup);
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context.EmitSttmp();
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}
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private static void EmitWBackIfNeeded(ILEmitterCtx context)
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{
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// Check whenever the current OpCode has post-indexed write back, if so write it.
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// Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both.
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if (context.CurrOp is OpCodeMemImm64 op && op.WBack)
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{
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context.EmitLdtmp();
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if (op.PostIdx)
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{
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context.EmitLdc_I(op.Imm);
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context.Emit(OpCodes.Add);
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}
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context.EmitStint(op.Rn);
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}
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}
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}
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} |