mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-10 17:58:50 +02:00
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
475 lines
No EOL
15 KiB
C#
475 lines
No EOL
15 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.IntermediateRepresentation;
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics.X86;
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namespace ChocolArm64.Instructions
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{
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static class InstEmitMemoryHelper
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{
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private static int _tempIntAddress = ILEmitterCtx.GetIntTempIndex();
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private static int _tempIntValue = ILEmitterCtx.GetIntTempIndex();
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private static int _tempIntPtAddr = ILEmitterCtx.GetIntTempIndex();
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private static int _tempVecValue = ILEmitterCtx.GetVecTempIndex();
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private enum Extension
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{
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Zx,
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Sx32,
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Sx64
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}
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public static void EmitReadZxCall(ILEmitterCtx context, int size)
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{
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EmitReadCall(context, Extension.Zx, size);
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}
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public static void EmitReadSx32Call(ILEmitterCtx context, int size)
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{
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EmitReadCall(context, Extension.Sx32, size);
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}
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public static void EmitReadSx64Call(ILEmitterCtx context, int size)
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{
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EmitReadCall(context, Extension.Sx64, size);
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}
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private static void EmitReadCall(ILEmitterCtx context, Extension ext, int size)
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{
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// Save the address into a temp.
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context.EmitStint(_tempIntAddress);
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bool isSimd = IsSimd(context);
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if (size < 0 || size > (isSimd ? 4 : 3))
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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if (isSimd)
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{
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if (context.Tier == TranslationTier.Tier0 || !Sse2.IsSupported || size < 2)
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{
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EmitReadVectorFallback(context, size);
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}
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else
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{
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EmitReadVector(context, size);
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}
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}
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else
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{
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if (context.Tier == TranslationTier.Tier0)
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{
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EmitReadIntFallback(context, size);
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}
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else
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{
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EmitReadInt(context, size);
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}
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}
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if (!isSimd)
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{
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if (ext == Extension.Sx32 ||
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ext == Extension.Sx64)
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{
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switch (size)
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{
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case 0: context.Emit(OpCodes.Conv_I1); break;
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case 1: context.Emit(OpCodes.Conv_I2); break;
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case 2: context.Emit(OpCodes.Conv_I4); break;
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}
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}
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if (size < 3)
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{
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context.Emit(ext == Extension.Sx64
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? OpCodes.Conv_I8
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: OpCodes.Conv_U8);
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}
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}
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}
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public static void EmitWriteCall(ILEmitterCtx context, int size)
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{
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bool isSimd = IsSimd(context);
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// Save the value into a temp.
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if (isSimd)
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{
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context.EmitStvec(_tempVecValue);
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}
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else
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{
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context.EmitStint(_tempIntValue);
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}
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// Save the address into a temp.
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context.EmitStint(_tempIntAddress);
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if (size < 0 || size > (isSimd ? 4 : 3))
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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if (isSimd)
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{
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if (context.Tier == TranslationTier.Tier0 || !Sse2.IsSupported || size < 2)
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{
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EmitWriteVectorFallback(context, size);
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}
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else
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{
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EmitWriteVector(context, size);
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}
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}
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else
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{
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if (context.Tier == TranslationTier.Tier0)
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{
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EmitWriteIntFallback(context, size);
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}
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else
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{
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EmitWriteInt(context, size);
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}
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}
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}
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private static bool IsSimd(ILEmitterCtx context)
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{
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return context.CurrOp is IOpCodeSimd64 &&
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!(context.CurrOp is OpCodeSimdMemMs64 ||
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context.CurrOp is OpCodeSimdMemSs64);
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}
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private static void EmitReadInt(ILEmitterCtx context, int size)
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{
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EmitAddressCheck(context, size);
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ILLabel lblFastPath = new ILLabel();
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ILLabel lblSlowPath = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(OpCodes.Brfalse_S, lblFastPath);
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context.MarkLabel(lblSlowPath);
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EmitReadIntFallback(context, size);
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context.Emit(OpCodes.Br, lblEnd);
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context.MarkLabel(lblFastPath);
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EmitPtPointerLoad(context, lblSlowPath);
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switch (size)
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{
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case 0: context.Emit(OpCodes.Ldind_U1); break;
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case 1: context.Emit(OpCodes.Ldind_U2); break;
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case 2: context.Emit(OpCodes.Ldind_U4); break;
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case 3: context.Emit(OpCodes.Ldind_I8); break;
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}
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context.MarkLabel(lblEnd);
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}
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private static void EmitReadVector(ILEmitterCtx context, int size)
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{
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EmitAddressCheck(context, size);
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ILLabel lblFastPath = new ILLabel();
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ILLabel lblSlowPath = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(OpCodes.Brfalse_S, lblFastPath);
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context.MarkLabel(lblSlowPath);
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EmitReadVectorFallback(context, size);
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context.Emit(OpCodes.Br, lblEnd);
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context.MarkLabel(lblFastPath);
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EmitPtPointerLoad(context, lblSlowPath);
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switch (size)
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{
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case 2: context.EmitCall(typeof(Sse), nameof(Sse.LoadScalarVector128)); break;
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case 3:
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{
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Type[] types = new Type[] { typeof(double*) };
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.LoadScalarVector128), types));
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break;
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}
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case 4: context.EmitCall(typeof(Sse), nameof(Sse.LoadAlignedVector128)); break;
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throw new InvalidOperationException($"Invalid vector load size of {1 << size} bytes.");
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}
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context.MarkLabel(lblEnd);
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}
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private static void EmitWriteInt(ILEmitterCtx context, int size)
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{
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EmitAddressCheck(context, size);
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ILLabel lblFastPath = new ILLabel();
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ILLabel lblSlowPath = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(OpCodes.Brfalse_S, lblFastPath);
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context.MarkLabel(lblSlowPath);
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EmitWriteIntFallback(context, size);
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context.Emit(OpCodes.Br, lblEnd);
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context.MarkLabel(lblFastPath);
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EmitPtPointerLoad(context, lblSlowPath);
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context.EmitLdint(_tempIntValue);
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if (size < 3)
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{
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context.Emit(OpCodes.Conv_U4);
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}
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switch (size)
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{
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case 0: context.Emit(OpCodes.Stind_I1); break;
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case 1: context.Emit(OpCodes.Stind_I2); break;
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case 2: context.Emit(OpCodes.Stind_I4); break;
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case 3: context.Emit(OpCodes.Stind_I8); break;
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}
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context.MarkLabel(lblEnd);
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}
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private static void EmitWriteVector(ILEmitterCtx context, int size)
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{
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EmitAddressCheck(context, size);
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ILLabel lblFastPath = new ILLabel();
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ILLabel lblSlowPath = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.Emit(OpCodes.Brfalse_S, lblFastPath);
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context.MarkLabel(lblSlowPath);
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EmitWriteVectorFallback(context, size);
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context.Emit(OpCodes.Br, lblEnd);
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context.MarkLabel(lblFastPath);
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EmitPtPointerLoad(context, lblSlowPath);
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context.EmitLdvec(_tempVecValue);
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switch (size)
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{
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case 2: context.EmitCall(typeof(Sse), nameof(Sse.StoreScalar)); break;
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case 3: context.EmitCall(typeof(Sse2), nameof(Sse2.StoreScalar)); break;
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case 4: context.EmitCall(typeof(Sse), nameof(Sse.StoreAligned)); break;
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default: throw new InvalidOperationException($"Invalid vector store size of {1 << size} bytes.");
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}
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context.MarkLabel(lblEnd);
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}
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private static void EmitAddressCheck(ILEmitterCtx context, int size)
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{
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long addressCheckMask = ~(context.Memory.AddressSpaceSize - 1);
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addressCheckMask |= (1u << size) - 1;
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context.EmitLdint(_tempIntAddress);
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context.EmitLdc_I(addressCheckMask);
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context.Emit(OpCodes.And);
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}
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private static void EmitPtPointerLoad(ILEmitterCtx context, ILLabel lblFallbackPath)
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{
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context.EmitLdc_I8(context.Memory.PageTable.ToInt64());
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context.Emit(OpCodes.Conv_I);
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int bit = MemoryManager.PageBits;
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do
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{
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context.EmitLdint(_tempIntAddress);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U8);
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}
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context.EmitLsr(bit);
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bit += context.Memory.PtLevelBits;
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if (bit < context.Memory.AddressSpaceBits)
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{
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context.EmitLdc_I8(context.Memory.PtLevelMask);
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context.Emit(OpCodes.And);
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}
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context.EmitLdc_I8(IntPtr.Size);
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context.Emit(OpCodes.Mul);
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context.Emit(OpCodes.Conv_I);
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context.Emit(OpCodes.Add);
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context.Emit(OpCodes.Ldind_I);
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}
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while (bit < context.Memory.AddressSpaceBits);
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if (!context.Memory.HasWriteWatchSupport)
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{
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context.Emit(OpCodes.Conv_U8);
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context.EmitStint(_tempIntPtAddr);
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context.EmitLdint(_tempIntPtAddr);
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context.EmitLdc_I8(MemoryManager.PteFlagsMask);
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context.Emit(OpCodes.And);
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context.Emit(OpCodes.Brtrue, lblFallbackPath);
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context.EmitLdint(_tempIntPtAddr);
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context.Emit(OpCodes.Conv_I);
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}
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context.EmitLdint(_tempIntAddress);
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context.EmitLdc_I(MemoryManager.PageMask);
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context.Emit(OpCodes.And);
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context.Emit(OpCodes.Conv_I);
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context.Emit(OpCodes.Add);
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}
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private static void EmitReadIntFallback(ILEmitterCtx context, int size)
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{
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdint(_tempIntAddress);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U8);
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}
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string fallbackMethodName = null;
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switch (size)
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{
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case 0: fallbackMethodName = nameof(MemoryManager.ReadByte); break;
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case 1: fallbackMethodName = nameof(MemoryManager.ReadUInt16); break;
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case 2: fallbackMethodName = nameof(MemoryManager.ReadUInt32); break;
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case 3: fallbackMethodName = nameof(MemoryManager.ReadUInt64); break;
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}
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context.EmitCall(typeof(MemoryManager), fallbackMethodName);
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}
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private static void EmitReadVectorFallback(ILEmitterCtx context, int size)
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{
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdint(_tempIntAddress);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U8);
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}
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string fallbackMethodName = null;
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switch (size)
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{
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case 0: fallbackMethodName = nameof(MemoryManager.ReadVector8); break;
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case 1: fallbackMethodName = nameof(MemoryManager.ReadVector16); break;
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case 2: fallbackMethodName = nameof(MemoryManager.ReadVector32); break;
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case 3: fallbackMethodName = nameof(MemoryManager.ReadVector64); break;
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case 4: fallbackMethodName = nameof(MemoryManager.ReadVector128); break;
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}
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context.EmitCall(typeof(MemoryManager), fallbackMethodName);
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}
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private static void EmitWriteIntFallback(ILEmitterCtx context, int size)
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{
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdint(_tempIntAddress);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U8);
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}
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context.EmitLdint(_tempIntValue);
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if (size < 3)
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{
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context.Emit(OpCodes.Conv_U4);
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}
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string fallbackMethodName = null;
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switch (size)
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{
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case 0: fallbackMethodName = nameof(MemoryManager.WriteByte); break;
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case 1: fallbackMethodName = nameof(MemoryManager.WriteUInt16); break;
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case 2: fallbackMethodName = nameof(MemoryManager.WriteUInt32); break;
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case 3: fallbackMethodName = nameof(MemoryManager.WriteUInt64); break;
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}
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context.EmitCall(typeof(MemoryManager), fallbackMethodName);
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}
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private static void EmitWriteVectorFallback(ILEmitterCtx context, int size)
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{
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdint(_tempIntAddress);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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context.Emit(OpCodes.Conv_U8);
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}
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context.EmitLdvec(_tempVecValue);
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string fallbackMethodName = null;
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switch (size)
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{
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case 0: fallbackMethodName = nameof(MemoryManager.WriteVector8); break;
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case 1: fallbackMethodName = nameof(MemoryManager.WriteVector16); break;
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case 2: fallbackMethodName = nameof(MemoryManager.WriteVector32); break;
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case 3: fallbackMethodName = nameof(MemoryManager.WriteVector64); break;
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case 4: fallbackMethodName = nameof(MemoryManager.WriteVector128Internal); break;
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}
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context.EmitCall(typeof(MemoryManager), fallbackMethodName);
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}
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}
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} |