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https://github.com/Ryujinx/Ryujinx.git
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* Turn `MemoryOperand` into a struct * Remove `IntrinsicOperation` * Remove `PhiNode` * Remove `Node` * Turn `Operand` into a struct * Turn `Operation` into a struct * Clean up pool management methods * Add `Arena` allocator * Move `OperationHelper` to `Operation.Factory` * Move `OperandHelper` to `Operand.Factory` * Optimize `Operation` a bit * Fix `Arena` initialization * Rename `NativeList<T>` to `ArenaList<T>` * Reduce `Operand` size from 88 to 56 bytes * Reduce `Operation` size from 56 to 40 bytes * Add optimistic interning of Register & Constant operands * Optimize `RegisterUsage` pass a bit * Optimize `RemoveUnusedNodes` pass a bit Iterating in reverse-order allows killing dependency chains in a single pass. * Fix PPTC symbols * Optimize `BasicBlock` a bit Reduce allocations from `_successor` & `DominanceFrontiers` * Fix `Operation` resize * Make `Arena` expandable Change the arena allocator to be expandable by allocating in pages, with some of them being pooled. Currently 32 pages are pooled. An LRU removal mechanism should probably be added to it. Apparently MHR can allocate bitmaps large enough to exceed the 16MB limit for the type. * Move `Arena` & `ArenaList` to `Common` * Remove `ThreadStaticPool` & co * Add `PhiOperation` * Reduce `Operand` size from 56 from 48 bytes * Add linear-probing to `Operand` intern table * Optimize `HybridAllocator` a bit * Add `Allocators` class * Tune `ArenaAllocator` sizes * Add page removal mechanism to `ArenaAllocator` Remove pages which have not been used for more than 5s after each reset. I am on fence if this would be better using a Gen2 callback object like the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right now if a large translation happens, the pages will be freed only after a reset. This reset may not happen for a while because no new translation is hit, but the arena base sizes are rather small. * Fix `OOM` when allocating larger than page size in `ArenaAllocator` Tweak resizing mechanism for Operand.Uses and Assignemnts. * Optimize `Optimizer` a bit * Optimize `Operand.Add<T>/Remove<T>` a bit * Clean up `PreAllocator` * Fix phi insertion order Reduce codegen diffs. * Fix code alignment * Use new heuristics for degree of parallelism * Suppress warnings * Address gdkchan's feedback Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that `Operand.Value` should usually not be modified directly. * Add fast path to `ArenaAllocator` * Assembly for `ArenaAllocator.Allocate(ulong)`: .L0: mov rax, [rcx+0x18] lea r8, [rax+rdx] cmp r8, [rcx+0x10] ja short .L2 .L1: mov rdx, [rcx+8] add rax, [rdx+8] mov [rcx+0x18], r8 ret .L2: jmp ArenaAllocator.AllocateSlow(UInt64) A few variable/field had to be changed to ulong so that RyuJIT avoids emitting zero-extends. * Implement a new heuristic to free pooled pages. If an arena is used often, it is more likely that its pages will be needed, so the pages are kept for longer (e.g: during PPTC rebuild or burst sof compilations). If is not used often, then it is more likely that its pages will not be needed (e.g: after PPTC rebuild or bursts of compilations). * Address riperiperi's feedback * Use `EqualityComparer<T>` in `IntrusiveList<T>` Avoids a potential GC hole in `Equals(T, T)`.
248 lines
No EOL
8.6 KiB
C#
248 lines
No EOL
8.6 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using System;
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using System.Collections.Generic;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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using static ARMeilleure.IntermediateRepresentation.Operation.Factory;
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namespace ARMeilleure.CodeGen.RegisterAllocators
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{
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class CopyResolver
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{
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private class ParallelCopy
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{
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private struct Copy
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{
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public Register Dest { get; }
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public Register Source { get; }
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public OperandType Type { get; }
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public Copy(Register dest, Register source, OperandType type)
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{
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Dest = dest;
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Source = source;
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Type = type;
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}
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}
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private List<Copy> _copies;
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public int Count => _copies.Count;
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public ParallelCopy()
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{
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_copies = new List<Copy>();
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}
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public void AddCopy(Register dest, Register source, OperandType type)
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{
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_copies.Add(new Copy(dest, source, type));
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}
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public void Sequence(List<Operation> sequence)
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{
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Dictionary<Register, Register> locations = new Dictionary<Register, Register>();
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Dictionary<Register, Register> sources = new Dictionary<Register, Register>();
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Dictionary<Register, OperandType> types = new Dictionary<Register, OperandType>();
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Queue<Register> pendingQueue = new Queue<Register>();
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Queue<Register> readyQueue = new Queue<Register>();
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foreach (Copy copy in _copies)
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{
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locations[copy.Source] = copy.Source;
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sources[copy.Dest] = copy.Source;
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types[copy.Dest] = copy.Type;
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pendingQueue.Enqueue(copy.Dest);
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}
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foreach (Copy copy in _copies)
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{
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// If the destination is not used anywhere, we can assign it immediately.
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if (!locations.ContainsKey(copy.Dest))
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{
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readyQueue.Enqueue(copy.Dest);
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}
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}
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while (pendingQueue.TryDequeue(out Register current))
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{
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Register copyDest;
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Register origSource;
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Register copySource;
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while (readyQueue.TryDequeue(out copyDest))
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{
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origSource = sources[copyDest];
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copySource = locations[origSource];
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OperandType type = types[copyDest];
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EmitCopy(sequence, GetRegister(copyDest, type), GetRegister(copySource, type));
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locations[origSource] = copyDest;
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if (origSource == copySource && sources.ContainsKey(origSource))
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{
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readyQueue.Enqueue(origSource);
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}
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}
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copyDest = current;
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origSource = sources[copyDest];
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copySource = locations[origSource];
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if (copyDest != copySource)
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{
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OperandType type = types[copyDest];
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type = type.IsInteger() ? OperandType.I64 : OperandType.V128;
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EmitXorSwap(sequence, GetRegister(copyDest, type), GetRegister(copySource, type));
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locations[origSource] = copyDest;
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Register swapOther = copySource;
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if (copyDest != locations[sources[copySource]])
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{
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// Find the other swap destination register.
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// To do that, we search all the pending registers, and pick
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// the one where the copy source register is equal to the
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// current destination register being processed (copyDest).
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foreach (Register pending in pendingQueue)
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{
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// Is this a copy of pending <- copyDest?
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if (copyDest == locations[sources[pending]])
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{
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swapOther = pending;
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break;
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}
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}
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}
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// The value that was previously at "copyDest" now lives on
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// "copySource" thanks to the swap, now we need to update the
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// location for the next copy that is supposed to copy the value
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// that used to live on "copyDest".
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locations[sources[swapOther]] = copySource;
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}
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}
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}
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private static void EmitCopy(List<Operation> sequence, Operand x, Operand y)
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{
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sequence.Add(Operation(Instruction.Copy, x, y));
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}
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private static void EmitXorSwap(List<Operation> sequence, Operand x, Operand y)
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{
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sequence.Add(Operation(Instruction.BitwiseExclusiveOr, x, x, y));
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sequence.Add(Operation(Instruction.BitwiseExclusiveOr, y, y, x));
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sequence.Add(Operation(Instruction.BitwiseExclusiveOr, x, x, y));
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}
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}
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private Queue<Operation> _fillQueue = new Queue<Operation>();
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private Queue<Operation> _spillQueue = new Queue<Operation>();
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private ParallelCopy _parallelCopy;
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public bool HasCopy { get; private set; }
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public CopyResolver()
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{
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_fillQueue = new Queue<Operation>();
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_spillQueue = new Queue<Operation>();
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_parallelCopy = new ParallelCopy();
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}
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public void AddSplit(LiveInterval left, LiveInterval right)
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{
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if (left.Local != right.Local)
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{
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throw new ArgumentException("Intervals of different variables are not allowed.");
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}
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OperandType type = left.Local.Type;
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if (left.IsSpilled && !right.IsSpilled)
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{
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// Move from the stack to a register.
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AddSplitFill(left, right, type);
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}
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else if (!left.IsSpilled && right.IsSpilled)
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{
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// Move from a register to the stack.
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AddSplitSpill(left, right, type);
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}
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else if (!left.IsSpilled && !right.IsSpilled && left.Register != right.Register)
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{
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// Move from one register to another.
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AddSplitCopy(left, right, type);
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}
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else if (left.SpillOffset != right.SpillOffset)
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{
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// This would be the stack-to-stack move case, but this is not supported.
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throw new ArgumentException("Both intervals were spilled.");
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}
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}
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private void AddSplitFill(LiveInterval left, LiveInterval right, OperandType type)
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{
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Operand register = GetRegister(right.Register, type);
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Operand offset = Const(left.SpillOffset);
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_fillQueue.Enqueue(Operation(Instruction.Fill, register, offset));
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HasCopy = true;
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}
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private void AddSplitSpill(LiveInterval left, LiveInterval right, OperandType type)
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{
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Operand offset = Const(right.SpillOffset);
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Operand register = GetRegister(left.Register, type);
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_spillQueue.Enqueue(Operation(Instruction.Spill, default, offset, register));
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HasCopy = true;
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}
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private void AddSplitCopy(LiveInterval left, LiveInterval right, OperandType type)
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{
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_parallelCopy.AddCopy(right.Register, left.Register, type);
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HasCopy = true;
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}
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public Operation[] Sequence()
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{
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List<Operation> sequence = new List<Operation>();
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while (_spillQueue.TryDequeue(out Operation spillOp))
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{
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sequence.Add(spillOp);
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}
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_parallelCopy.Sequence(sequence);
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while (_fillQueue.TryDequeue(out Operation fillOp))
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{
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sequence.Add(fillOp);
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}
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return sequence.ToArray();
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}
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private static Operand GetRegister(Register reg, OperandType type)
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{
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return Register(reg.Index, reg.Type, type);
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}
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}
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} |