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https://github.com/Ryujinx/Ryujinx.git
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382 lines
13 KiB
C#
382 lines
13 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using System;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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using static ARMeilleure.IntermediateRepresentation.OperationHelper;
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namespace ARMeilleure.Translation
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{
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static class RegisterUsage
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{
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private const int RegsCount = 32;
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private const int RegsMask = RegsCount - 1;
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private struct RegisterMask : IEquatable<RegisterMask>
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{
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public long IntMask { get; set; }
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public long VecMask { get; set; }
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public RegisterMask(long intMask, long vecMask)
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{
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IntMask = intMask;
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VecMask = vecMask;
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}
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public static RegisterMask operator &(RegisterMask x, RegisterMask y)
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{
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return new RegisterMask(x.IntMask & y.IntMask, x.VecMask & y.VecMask);
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}
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public static RegisterMask operator |(RegisterMask x, RegisterMask y)
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{
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return new RegisterMask(x.IntMask | y.IntMask, x.VecMask | y.VecMask);
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}
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public static RegisterMask operator ~(RegisterMask x)
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{
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return new RegisterMask(~x.IntMask, ~x.VecMask);
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}
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public static bool operator ==(RegisterMask x, RegisterMask y)
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{
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return x.Equals(y);
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}
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public static bool operator !=(RegisterMask x, RegisterMask y)
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{
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return !x.Equals(y);
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}
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public override bool Equals(object obj)
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{
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return obj is RegisterMask regMask && Equals(regMask);
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}
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public bool Equals(RegisterMask other)
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{
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return IntMask == other.IntMask && VecMask == other.VecMask;
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}
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public override int GetHashCode()
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{
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return HashCode.Combine(IntMask, VecMask);
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}
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}
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public static void RunPass(ControlFlowGraph cfg, ExecutionMode mode)
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{
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// Compute local register inputs and outputs used inside blocks.
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RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] localOutputs = new RegisterMask[cfg.Blocks.Count];
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for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext)
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{
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for (Node node = block.Operations.First; node != null; node = node.ListNext)
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{
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Operation operation = node as Operation;
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for (int srcIndex = 0; srcIndex < operation.SourcesCount; srcIndex++)
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{
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Operand source = operation.GetSource(srcIndex);
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if (source.Kind != OperandKind.Register)
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{
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continue;
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}
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Register register = source.GetRegister();
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localInputs[block.Index] |= GetMask(register) & ~localOutputs[block.Index];
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}
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if (operation.Destination != null && operation.Destination.Kind == OperandKind.Register)
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{
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localOutputs[block.Index] |= GetMask(operation.Destination.GetRegister());
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}
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}
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}
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// Compute global register inputs and outputs used across blocks.
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RegisterMask[] globalCmnOutputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] globalOutputs = new RegisterMask[cfg.Blocks.Count];
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bool modified;
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bool firstPass = true;
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do
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{
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modified = false;
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// Compute register outputs.
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for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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if (block.Predecessors.Count != 0 && !HasContextLoad(block))
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{
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BasicBlock predecessor = block.Predecessors[0];
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RegisterMask cmnOutputs = localOutputs[predecessor.Index] | globalCmnOutputs[predecessor.Index];
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RegisterMask outputs = globalOutputs[predecessor.Index];
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for (int pIndex = 1; pIndex < block.Predecessors.Count; pIndex++)
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{
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predecessor = block.Predecessors[pIndex];
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cmnOutputs &= localOutputs[predecessor.Index] | globalCmnOutputs[predecessor.Index];
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outputs |= globalOutputs[predecessor.Index];
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}
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globalInputs[block.Index] |= outputs & ~cmnOutputs;
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if (!firstPass)
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{
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cmnOutputs &= globalCmnOutputs[block.Index];
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}
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if (Exchange(globalCmnOutputs, block.Index, cmnOutputs))
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{
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modified = true;
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}
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outputs |= localOutputs[block.Index];
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if (Exchange(globalOutputs, block.Index, globalOutputs[block.Index] | outputs))
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{
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modified = true;
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}
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}
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else if (Exchange(globalOutputs, block.Index, localOutputs[block.Index]))
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{
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modified = true;
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}
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}
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// Compute register inputs.
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for (int index = 0; index < cfg.PostOrderBlocks.Length; index++)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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RegisterMask inputs = localInputs[block.Index];
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for (int i = 0; i < block.SuccessorCount; i++)
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{
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inputs |= globalInputs[block.GetSuccessor(i).Index];
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}
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inputs &= ~globalCmnOutputs[block.Index];
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if (Exchange(globalInputs, block.Index, globalInputs[block.Index] | inputs))
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{
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modified = true;
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}
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}
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firstPass = false;
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}
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while (modified);
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// Insert load and store context instructions where needed.
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for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext)
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{
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bool hasContextLoad = HasContextLoad(block);
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if (hasContextLoad)
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{
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block.Operations.Remove(block.Operations.First);
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}
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// The only block without any predecessor should be the entry block.
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// It always needs a context load as it is the first block to run.
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if (block.Predecessors.Count == 0 || hasContextLoad)
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{
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LoadLocals(block, globalInputs[block.Index].VecMask, RegisterType.Vector, mode);
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LoadLocals(block, globalInputs[block.Index].IntMask, RegisterType.Integer, mode);
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}
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bool hasContextStore = HasContextStore(block);
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if (hasContextStore)
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{
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block.Operations.Remove(block.Operations.Last);
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}
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if (EndsWithReturn(block) || hasContextStore)
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{
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StoreLocals(block, globalOutputs[block.Index].IntMask, RegisterType.Integer, mode);
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StoreLocals(block, globalOutputs[block.Index].VecMask, RegisterType.Vector, mode);
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}
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}
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}
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private static bool HasContextLoad(BasicBlock block)
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{
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return StartsWith(block, Instruction.LoadFromContext) && block.Operations.First.SourcesCount == 0;
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}
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private static bool HasContextStore(BasicBlock block)
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{
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return EndsWith(block, Instruction.StoreToContext) && block.GetLastOp().SourcesCount == 0;
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}
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private static bool StartsWith(BasicBlock block, Instruction inst)
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{
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if (block.Operations.Count == 0)
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{
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return false;
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}
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return block.Operations.First is Operation operation && operation.Instruction == inst;
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}
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private static bool EndsWith(BasicBlock block, Instruction inst)
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{
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if (block.Operations.Count == 0)
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{
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return false;
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}
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return block.Operations.Last is Operation operation && operation.Instruction == inst;
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}
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private static RegisterMask GetMask(Register register)
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{
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long intMask = 0;
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long vecMask = 0;
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switch (register.Type)
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{
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case RegisterType.Flag: intMask = (1L << RegsCount) << register.Index; break;
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case RegisterType.Integer: intMask = 1L << register.Index; break;
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case RegisterType.FpFlag: vecMask = (1L << RegsCount) << register.Index; break;
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case RegisterType.Vector: vecMask = 1L << register.Index; break;
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}
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return new RegisterMask(intMask, vecMask);
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}
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private static bool Exchange(RegisterMask[] masks, int blkIndex, RegisterMask value)
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{
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RegisterMask oldValue = masks[blkIndex];
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masks[blkIndex] = value;
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return oldValue != value;
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}
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private static void LoadLocals(BasicBlock block, long inputs, RegisterType baseType, ExecutionMode mode)
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{
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Operand arg0 = Local(OperandType.I64);
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for (int bit = 63; bit >= 0; bit--)
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{
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long mask = 1L << bit;
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if ((inputs & mask) == 0)
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{
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continue;
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}
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Operand dest = GetRegFromBit(bit, baseType, mode);
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long offset = NativeContext.GetRegisterOffset(dest.GetRegister());
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Operand addr = Local(OperandType.I64);
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Operation loadOp = Operation(Instruction.Load, dest, addr);
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block.Operations.AddFirst(loadOp);
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Operation calcOffsOp = Operation(Instruction.Add, addr, arg0, Const(offset));
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block.Operations.AddFirst(calcOffsOp);
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}
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Operation loadArg0 = Operation(Instruction.LoadArgument, arg0, Const(0));
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block.Operations.AddFirst(loadArg0);
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}
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private static void StoreLocals(BasicBlock block, long outputs, RegisterType baseType, ExecutionMode mode)
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{
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Operand arg0 = Local(OperandType.I64);
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Operation loadArg0 = Operation(Instruction.LoadArgument, arg0, Const(0));
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block.Append(loadArg0);
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for (int bit = 0; bit < 64; bit++)
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{
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long mask = 1L << bit;
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if ((outputs & mask) == 0)
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{
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continue;
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}
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Operand source = GetRegFromBit(bit, baseType, mode);
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long offset = NativeContext.GetRegisterOffset(source.GetRegister());
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Operand addr = Local(OperandType.I64);
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Operation calcOffsOp = Operation(Instruction.Add, addr, arg0, Const(offset));
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block.Append(calcOffsOp);
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Operation storeOp = Operation(Instruction.Store, null, addr, source);
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block.Append(storeOp);
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}
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}
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private static Operand GetRegFromBit(int bit, RegisterType baseType, ExecutionMode mode)
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{
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if (bit < RegsCount)
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{
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return OperandHelper.Register(bit, baseType, GetOperandType(baseType, mode));
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}
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else if (baseType == RegisterType.Integer)
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{
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return OperandHelper.Register(bit & RegsMask, RegisterType.Flag, OperandType.I32);
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}
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else if (baseType == RegisterType.Vector)
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{
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return OperandHelper.Register(bit & RegsMask, RegisterType.FpFlag, OperandType.I32);
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(bit));
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}
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}
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private static OperandType GetOperandType(RegisterType type, ExecutionMode mode)
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{
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switch (type)
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{
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case RegisterType.Flag: return OperandType.I32;
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case RegisterType.FpFlag: return OperandType.I32;
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case RegisterType.Integer: return (mode == ExecutionMode.Aarch64) ? OperandType.I64 : OperandType.I32;
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case RegisterType.Vector: return OperandType.V128;
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}
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throw new ArgumentException($"Invalid register type \"{type}\".");
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}
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private static bool EndsWithReturn(BasicBlock block)
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{
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if (!(block.GetLastOp() is Operation operation))
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{
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return false;
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}
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return operation.Instruction == Instruction.Return;
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}
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}
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} |