mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-19 23:28:42 +02:00
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure 😩
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
572 lines
18 KiB
C#
572 lines
18 KiB
C#
using ARMeilleure.Decoders;
|
|
using ARMeilleure.IntermediateRepresentation;
|
|
using ARMeilleure.Memory;
|
|
using ARMeilleure.Translation;
|
|
using System;
|
|
|
|
using static ARMeilleure.Instructions.InstEmitHelper;
|
|
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
|
|
|
|
namespace ARMeilleure.Instructions
|
|
{
|
|
static class InstEmitMemoryHelper
|
|
{
|
|
private enum Extension
|
|
{
|
|
Zx,
|
|
Sx32,
|
|
Sx64
|
|
}
|
|
|
|
public static void EmitLoadZx(ArmEmitterContext context, Operand address, int rt, int size)
|
|
{
|
|
EmitLoad(context, address, Extension.Zx, rt, size);
|
|
}
|
|
|
|
public static void EmitLoadSx32(ArmEmitterContext context, Operand address, int rt, int size)
|
|
{
|
|
EmitLoad(context, address, Extension.Sx32, rt, size);
|
|
}
|
|
|
|
public static void EmitLoadSx64(ArmEmitterContext context, Operand address, int rt, int size)
|
|
{
|
|
EmitLoad(context, address, Extension.Sx64, rt, size);
|
|
}
|
|
|
|
private static void EmitLoad(ArmEmitterContext context, Operand address, Extension ext, int rt, int size)
|
|
{
|
|
bool isSimd = IsSimd(context);
|
|
|
|
if ((uint)size > (isSimd ? 4 : 3))
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(size));
|
|
}
|
|
|
|
if (isSimd)
|
|
{
|
|
EmitReadVector(context, address, context.VectorZero(), rt, 0, size);
|
|
}
|
|
else
|
|
{
|
|
EmitReadInt(context, address, rt, size);
|
|
}
|
|
|
|
if (!isSimd)
|
|
{
|
|
Operand value = GetInt(context, rt);
|
|
|
|
if (ext == Extension.Sx32 || ext == Extension.Sx64)
|
|
{
|
|
OperandType destType = ext == Extension.Sx64 ? OperandType.I64 : OperandType.I32;
|
|
|
|
switch (size)
|
|
{
|
|
case 0: value = context.SignExtend8 (destType, value); break;
|
|
case 1: value = context.SignExtend16(destType, value); break;
|
|
case 2: value = context.SignExtend32(destType, value); break;
|
|
}
|
|
}
|
|
|
|
SetInt(context, rt, value);
|
|
}
|
|
}
|
|
|
|
public static void EmitLoadSimd(
|
|
ArmEmitterContext context,
|
|
Operand address,
|
|
Operand vector,
|
|
int rt,
|
|
int elem,
|
|
int size)
|
|
{
|
|
EmitReadVector(context, address, vector, rt, elem, size);
|
|
}
|
|
|
|
public static void EmitStore(ArmEmitterContext context, Operand address, int rt, int size)
|
|
{
|
|
bool isSimd = IsSimd(context);
|
|
|
|
if ((uint)size > (isSimd ? 4 : 3))
|
|
{
|
|
throw new ArgumentOutOfRangeException(nameof(size));
|
|
}
|
|
|
|
if (isSimd)
|
|
{
|
|
EmitWriteVector(context, address, rt, 0, size);
|
|
}
|
|
else
|
|
{
|
|
EmitWriteInt(context, address, rt, size);
|
|
}
|
|
}
|
|
|
|
public static void EmitStoreSimd(
|
|
ArmEmitterContext context,
|
|
Operand address,
|
|
int rt,
|
|
int elem,
|
|
int size)
|
|
{
|
|
EmitWriteVector(context, address, rt, elem, size);
|
|
}
|
|
|
|
private static bool IsSimd(ArmEmitterContext context)
|
|
{
|
|
return context.CurrOp is IOpCodeSimd &&
|
|
!(context.CurrOp is OpCodeSimdMemMs ||
|
|
context.CurrOp is OpCodeSimdMemSs);
|
|
}
|
|
|
|
private static void EmitReadInt(ArmEmitterContext context, Operand address, int rt, int size)
|
|
{
|
|
Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
|
|
|
|
Operand lblFastPath = Label();
|
|
Operand lblSlowPath = Label();
|
|
Operand lblEnd = Label();
|
|
|
|
context.BranchIfFalse(lblFastPath, isUnalignedAddr);
|
|
|
|
context.MarkLabel(lblSlowPath);
|
|
|
|
EmitReadIntFallback(context, address, rt, size);
|
|
|
|
context.Branch(lblEnd);
|
|
|
|
context.MarkLabel(lblFastPath);
|
|
|
|
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
|
|
|
|
Operand value = null;
|
|
|
|
switch (size)
|
|
{
|
|
case 0:
|
|
value = context.Load8(physAddr);
|
|
break;
|
|
|
|
case 1:
|
|
value = context.Load16(physAddr);
|
|
break;
|
|
|
|
case 2:
|
|
value = context.Load(OperandType.I32, physAddr);
|
|
break;
|
|
|
|
case 3:
|
|
value = context.Load(OperandType.I64, physAddr);
|
|
break;
|
|
}
|
|
|
|
SetInt(context, rt, value);
|
|
|
|
context.MarkLabel(lblEnd);
|
|
}
|
|
|
|
private static void EmitReadVector(
|
|
ArmEmitterContext context,
|
|
Operand address,
|
|
Operand vector,
|
|
int rt,
|
|
int elem,
|
|
int size)
|
|
{
|
|
Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
|
|
|
|
Operand lblFastPath = Label();
|
|
Operand lblSlowPath = Label();
|
|
Operand lblEnd = Label();
|
|
|
|
context.BranchIfFalse(lblFastPath, isUnalignedAddr);
|
|
|
|
context.MarkLabel(lblSlowPath);
|
|
|
|
EmitReadVectorFallback(context, address, vector, rt, elem, size);
|
|
|
|
context.Branch(lblEnd);
|
|
|
|
context.MarkLabel(lblFastPath);
|
|
|
|
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
|
|
|
|
Operand value = null;
|
|
|
|
switch (size)
|
|
{
|
|
case 0:
|
|
value = context.VectorInsert8(vector, context.Load8(physAddr), elem);
|
|
break;
|
|
|
|
case 1:
|
|
value = context.VectorInsert16(vector, context.Load16(physAddr), elem);
|
|
break;
|
|
|
|
case 2:
|
|
value = context.VectorInsert(vector, context.Load(OperandType.I32, physAddr), elem);
|
|
break;
|
|
|
|
case 3:
|
|
value = context.VectorInsert(vector, context.Load(OperandType.I64, physAddr), elem);
|
|
break;
|
|
|
|
case 4:
|
|
value = context.Load(OperandType.V128, physAddr);
|
|
break;
|
|
}
|
|
|
|
context.Copy(GetVec(rt), value);
|
|
|
|
context.MarkLabel(lblEnd);
|
|
}
|
|
|
|
private static Operand VectorCreate(ArmEmitterContext context, Operand value)
|
|
{
|
|
return context.VectorInsert(context.VectorZero(), value, 0);
|
|
}
|
|
|
|
private static void EmitWriteInt(ArmEmitterContext context, Operand address, int rt, int size)
|
|
{
|
|
Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
|
|
|
|
Operand lblFastPath = Label();
|
|
Operand lblSlowPath = Label();
|
|
Operand lblEnd = Label();
|
|
|
|
context.BranchIfFalse(lblFastPath, isUnalignedAddr);
|
|
|
|
context.MarkLabel(lblSlowPath);
|
|
|
|
EmitWriteIntFallback(context, address, rt, size);
|
|
|
|
context.Branch(lblEnd);
|
|
|
|
context.MarkLabel(lblFastPath);
|
|
|
|
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
|
|
|
|
Operand value = GetInt(context, rt);
|
|
|
|
if (size < 3 && value.Type == OperandType.I64)
|
|
{
|
|
value = context.ConvertI64ToI32(value);
|
|
}
|
|
|
|
switch (size)
|
|
{
|
|
case 0: context.Store8 (physAddr, value); break;
|
|
case 1: context.Store16(physAddr, value); break;
|
|
case 2: context.Store (physAddr, value); break;
|
|
case 3: context.Store (physAddr, value); break;
|
|
}
|
|
|
|
context.MarkLabel(lblEnd);
|
|
}
|
|
|
|
private static void EmitWriteVector(
|
|
ArmEmitterContext context,
|
|
Operand address,
|
|
int rt,
|
|
int elem,
|
|
int size)
|
|
{
|
|
Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
|
|
|
|
Operand lblFastPath = Label();
|
|
Operand lblSlowPath = Label();
|
|
Operand lblEnd = Label();
|
|
|
|
context.BranchIfFalse(lblFastPath, isUnalignedAddr);
|
|
|
|
context.MarkLabel(lblSlowPath);
|
|
|
|
EmitWriteVectorFallback(context, address, rt, elem, size);
|
|
|
|
context.Branch(lblEnd);
|
|
|
|
context.MarkLabel(lblFastPath);
|
|
|
|
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
|
|
|
|
Operand value = GetVec(rt);
|
|
|
|
switch (size)
|
|
{
|
|
case 0:
|
|
context.Store8(physAddr, context.VectorExtract8(value, elem));
|
|
break;
|
|
|
|
case 1:
|
|
context.Store16(physAddr, context.VectorExtract16(value, elem));
|
|
break;
|
|
|
|
case 2:
|
|
context.Store(physAddr, context.VectorExtract(OperandType.FP32, value, elem));
|
|
break;
|
|
|
|
case 3:
|
|
context.Store(physAddr, context.VectorExtract(OperandType.FP64, value, elem));
|
|
break;
|
|
|
|
case 4:
|
|
context.Store(physAddr, value);
|
|
break;
|
|
}
|
|
|
|
context.MarkLabel(lblEnd);
|
|
}
|
|
|
|
private static Operand EmitAddressCheck(ArmEmitterContext context, Operand address, int size)
|
|
{
|
|
long addressCheckMask = ~(context.Memory.AddressSpaceSize - 1);
|
|
|
|
addressCheckMask |= (1u << size) - 1;
|
|
|
|
return context.BitwiseAnd(address, Const(address.Type, addressCheckMask));
|
|
}
|
|
|
|
private static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblFallbackPath)
|
|
{
|
|
Operand pte = Const(context.Memory.PageTable.ToInt64());
|
|
|
|
int bit = MemoryManager.PageBits;
|
|
|
|
do
|
|
{
|
|
Operand addrPart = context.ShiftRightUI(address, Const(bit));
|
|
|
|
bit += context.Memory.PtLevelBits;
|
|
|
|
if (bit < context.Memory.AddressSpaceBits)
|
|
{
|
|
addrPart = context.BitwiseAnd(addrPart, Const(addrPart.Type, context.Memory.PtLevelMask));
|
|
}
|
|
|
|
Operand pteOffset = context.ShiftLeft(addrPart, Const(3));
|
|
|
|
if (pteOffset.Type == OperandType.I32)
|
|
{
|
|
pteOffset = context.ZeroExtend32(OperandType.I64, pteOffset);
|
|
}
|
|
|
|
Operand pteAddress = context.Add(pte, pteOffset);
|
|
|
|
pte = context.Load(OperandType.I64, pteAddress);
|
|
}
|
|
while (bit < context.Memory.AddressSpaceBits);
|
|
|
|
Operand hasFlagSet = context.BitwiseAnd(pte, Const((long)MemoryManager.PteFlagsMask));
|
|
|
|
context.BranchIfTrue(lblFallbackPath, hasFlagSet);
|
|
|
|
Operand pageOffset = context.BitwiseAnd(address, Const(address.Type, MemoryManager.PageMask));
|
|
|
|
if (pageOffset.Type == OperandType.I32)
|
|
{
|
|
pageOffset = context.ZeroExtend32(OperandType.I64, pageOffset);
|
|
}
|
|
|
|
Operand physAddr = context.Add(pte, pageOffset);
|
|
|
|
return physAddr;
|
|
}
|
|
|
|
private static void EmitReadIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
|
|
{
|
|
Delegate fallbackMethodDlg = null;
|
|
|
|
switch (size)
|
|
{
|
|
case 0: fallbackMethodDlg = new _U8_U64 (NativeInterface.ReadByte); break;
|
|
case 1: fallbackMethodDlg = new _U16_U64(NativeInterface.ReadUInt16); break;
|
|
case 2: fallbackMethodDlg = new _U32_U64(NativeInterface.ReadUInt32); break;
|
|
case 3: fallbackMethodDlg = new _U64_U64(NativeInterface.ReadUInt64); break;
|
|
}
|
|
|
|
SetInt(context, rt, context.Call(fallbackMethodDlg, address));
|
|
}
|
|
|
|
private static void EmitReadVectorFallback(
|
|
ArmEmitterContext context,
|
|
Operand address,
|
|
Operand vector,
|
|
int rt,
|
|
int elem,
|
|
int size)
|
|
{
|
|
Delegate fallbackMethodDlg = null;
|
|
|
|
switch (size)
|
|
{
|
|
case 0: fallbackMethodDlg = new _U8_U64 (NativeInterface.ReadByte); break;
|
|
case 1: fallbackMethodDlg = new _U16_U64 (NativeInterface.ReadUInt16); break;
|
|
case 2: fallbackMethodDlg = new _U32_U64 (NativeInterface.ReadUInt32); break;
|
|
case 3: fallbackMethodDlg = new _U64_U64 (NativeInterface.ReadUInt64); break;
|
|
case 4: fallbackMethodDlg = new _V128_U64(NativeInterface.ReadVector128); break;
|
|
}
|
|
|
|
Operand value = context.Call(fallbackMethodDlg, address);
|
|
|
|
switch (size)
|
|
{
|
|
case 0: value = context.VectorInsert8 (vector, value, elem); break;
|
|
case 1: value = context.VectorInsert16(vector, value, elem); break;
|
|
case 2: value = context.VectorInsert (vector, value, elem); break;
|
|
case 3: value = context.VectorInsert (vector, value, elem); break;
|
|
}
|
|
|
|
context.Copy(GetVec(rt), value);
|
|
}
|
|
|
|
private static void EmitWriteIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
|
|
{
|
|
Delegate fallbackMethodDlg = null;
|
|
|
|
switch (size)
|
|
{
|
|
case 0: fallbackMethodDlg = new _Void_U64_U8 (NativeInterface.WriteByte); break;
|
|
case 1: fallbackMethodDlg = new _Void_U64_U16(NativeInterface.WriteUInt16); break;
|
|
case 2: fallbackMethodDlg = new _Void_U64_U32(NativeInterface.WriteUInt32); break;
|
|
case 3: fallbackMethodDlg = new _Void_U64_U64(NativeInterface.WriteUInt64); break;
|
|
}
|
|
|
|
Operand value = GetInt(context, rt);
|
|
|
|
if (size < 3 && value.Type == OperandType.I64)
|
|
{
|
|
value = context.ConvertI64ToI32(value);
|
|
}
|
|
|
|
context.Call(fallbackMethodDlg, address, value);
|
|
}
|
|
|
|
private static void EmitWriteVectorFallback(
|
|
ArmEmitterContext context,
|
|
Operand address,
|
|
int rt,
|
|
int elem,
|
|
int size)
|
|
{
|
|
Delegate fallbackMethodDlg = null;
|
|
|
|
switch (size)
|
|
{
|
|
case 0: fallbackMethodDlg = new _Void_U64_U8 (NativeInterface.WriteByte); break;
|
|
case 1: fallbackMethodDlg = new _Void_U64_U16 (NativeInterface.WriteUInt16); break;
|
|
case 2: fallbackMethodDlg = new _Void_U64_U32 (NativeInterface.WriteUInt32); break;
|
|
case 3: fallbackMethodDlg = new _Void_U64_U64 (NativeInterface.WriteUInt64); break;
|
|
case 4: fallbackMethodDlg = new _Void_U64_V128(NativeInterface.WriteVector128); break;
|
|
}
|
|
|
|
Operand value = null;
|
|
|
|
if (size < 4)
|
|
{
|
|
switch (size)
|
|
{
|
|
case 0:
|
|
value = context.VectorExtract8(GetVec(rt), elem);
|
|
break;
|
|
|
|
case 1:
|
|
value = context.VectorExtract16(GetVec(rt), elem);
|
|
break;
|
|
|
|
case 2:
|
|
value = context.VectorExtract(OperandType.I32, GetVec(rt), elem);
|
|
break;
|
|
|
|
case 3:
|
|
value = context.VectorExtract(OperandType.I64, GetVec(rt), elem);
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
value = GetVec(rt);
|
|
}
|
|
|
|
context.Call(fallbackMethodDlg, address, value);
|
|
}
|
|
|
|
private static Operand GetInt(ArmEmitterContext context, int rt)
|
|
{
|
|
return context.CurrOp is OpCode32 ? GetIntA32(context, rt) : GetIntOrZR(context, rt);
|
|
}
|
|
|
|
private static void SetInt(ArmEmitterContext context, int rt, Operand value)
|
|
{
|
|
if (context.CurrOp is OpCode32)
|
|
{
|
|
SetIntA32(context, rt, value);
|
|
}
|
|
else
|
|
{
|
|
SetIntOrZR(context, rt, value);
|
|
}
|
|
}
|
|
|
|
// ARM32 helpers.
|
|
public static Operand GetMemM(ArmEmitterContext context, bool setCarry = true)
|
|
{
|
|
switch (context.CurrOp)
|
|
{
|
|
case OpCode32MemRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
|
|
|
|
case OpCode32MemReg op: return GetIntA32(context, op.Rm);
|
|
|
|
case OpCode32Mem op: return Const(op.Immediate);
|
|
|
|
case OpCode32SimdMemImm op: return Const(op.Immediate);
|
|
|
|
default: throw InvalidOpCodeType(context.CurrOp);
|
|
}
|
|
}
|
|
|
|
private static Exception InvalidOpCodeType(OpCode opCode)
|
|
{
|
|
return new InvalidOperationException($"Invalid OpCode type \"{opCode?.GetType().Name ?? "null"}\".");
|
|
}
|
|
|
|
public static Operand GetMShiftedByImmediate(ArmEmitterContext context, OpCode32MemRsImm op, bool setCarry)
|
|
{
|
|
Operand m = GetIntA32(context, op.Rm);
|
|
|
|
int shift = op.Immediate;
|
|
|
|
if (shift == 0)
|
|
{
|
|
switch (op.ShiftType)
|
|
{
|
|
case ShiftType.Lsr: shift = 32; break;
|
|
case ShiftType.Asr: shift = 32; break;
|
|
case ShiftType.Ror: shift = 1; break;
|
|
}
|
|
}
|
|
|
|
if (shift != 0)
|
|
{
|
|
setCarry &= false;
|
|
|
|
switch (op.ShiftType)
|
|
{
|
|
case ShiftType.Lsl: m = InstEmitAluHelper.GetLslC(context, m, setCarry, shift); break;
|
|
case ShiftType.Lsr: m = InstEmitAluHelper.GetLsrC(context, m, setCarry, shift); break;
|
|
case ShiftType.Asr: m = InstEmitAluHelper.GetAsrC(context, m, setCarry, shift); break;
|
|
case ShiftType.Ror:
|
|
if (op.Immediate != 0)
|
|
{
|
|
m = InstEmitAluHelper.GetRorC(context, m, setCarry, shift);
|
|
}
|
|
else
|
|
{
|
|
m = InstEmitAluHelper.GetRrxC(context, m, setCarry);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
return m;
|
|
}
|
|
}
|
|
} |