mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-20 07:38:42 +02:00
* Implement TEQ and MOV (Imm16)
* Initial work on A32 instructions + SVC. No tests yet, hangs in rtld.
* Implement CLZ, fix BFI and BFC
Now stops on SIMD initialization.
* Exclusive access instructions, fix to mul, system instructions.
Now gets to a break after SignalProcessWideKey64.
* Better impl of UBFX, add UDIV and SDIV
Now boots way further - now stuck on VMOV instruction.
* Many more instructions, start on SIMD and testing framework.
* Fix build issues
* svc: Rework 32 bit codepath
Fixing once and for all argument ordering issues.
* Fix 32 bits stacktrace
* hle debug: Add 32 bits dynamic section parsing
* Fix highCq mode, add many tests, fix some instruction bugs
Still suffers from critical malloc failure 😩
* Fix incorrect opcode decoders and a few more instructions.
* Add a few instructions and fix others. re-disable highCq for now.
Disabled the svc memory clear since i'm not sure about it.
* Fix build
* Fix typo in ordered/exclusive stores.
* Implement some more instructions, fix others.
Uxtab16/Sxtab16 are untested.
* Begin impl of pairwise, some other instructions.
* Add a few more instructions, a quick hack to fix svcs for now.
* Add tests and fix issues with VTRN, VZIP, VUZP
* Add a few more instructions, fix Vmul_1 encoding.
* Fix way too many instruction bugs, add tests for some of the more important ones.
* Fix HighCq, enable FastFP paths for some floating point instructions
(not entirely sure why these were disabled, so important to note this
commit exists)
Branching has been removed in A32 shifts until I figure out if it's
worth it
* Cleanup Part 1
There should be no functional change between these next few commits.
Should is the key word. (except for removing break handler)
* Implement 32 bits syscalls
Co-authored-by: riperiperi <rhy3756547@hotmail.com>
Implement all 32 bits counterparts of the 64 bits syscalls we currently
have.
* Refactor part 2: Move index/subindex logic to Operand
May have inadvertently fixed one (1) bug
* Add FlushProcessDataCache32
* Address jd's comments
* Remove 16 bit encodings from OpCodeTable
Still need to catch some edge cases (operands that use the "F" flag) and
make Q encodings with non-even indexes undefined.
* Correct Fpscr handling for FP vector slow paths
WIP
* Add StandardFPSCRValue behaviour for all Arithmetic instructions
* Add StandardFPSCRValue behaviour to compare instructions.
* Force passing of fpcr to FPProcessException and FPUnpack.
Reduces potential for code error significantly
* OpCode cleanup
* Remove urgency from DMB comment in MRRC
DMB is currently a no-op via the instruction, so it should likely still
be a no-op here.
* Test Cleanup
* Fix FPDefaultNaN on Ryzen CPUs
* Improve some tests, fix some shift instructions, add slow path for Vadd
* Fix Typo
* More test cleanup
* Flip order of Fx and index, to indicate that the operand's is the "base"
* Remove Simd32 register type, use Int32 and Int64 for scalars like A64 does.
* Reintroduce alignment to DecoderHelper (removed by accident)
* One more realign as reading diffs is hard
* Use I32 registers in A32 (part 2)
Swap default integer register type based on current execution mode.
* FPSCR flags as Registers (part 1)
Still need to change NativeContext and ExecutionContext to allow
getting/setting with the flag values.
* Use I32 registers in A32 (part 1)
* FPSCR flags as registers (part 2)
Only CMP flags are on the registers right now. It could be useful to use
more of the space in non-fast-float when implementing A32 flags
accurately in the fast path.
* Address Feedback
* Correct FP->Int behaviour (should saturate)
* Make branches made by writing to PC eligible for Rejit
Greatly improves performance in most games.
* Remove unused branching for Vtbl
* RejitRequest as a class rather than a tuple
Makes a lot more sense than storing tuples on a dictionary.
* Add VMOVN, VSHR (imm), VSHRN (imm) and related tests
* Re-order InstEmitSystem32
Alphabetical sorting.
* Address Feedback
Feedback from Ac_K, remove and sort usings.
* Address Feedback 2
* Address Feedback from LDj3SNuD
Opcode table reordered to have alphabetical sorting within groups,
Vmaxnm and Vminnm have split names to be less ambiguous, SoftFloat nits,
Test nits and Test simplification with ValueSource.
* Add Debug Asserts to A32 helpers
Mainly to prevent the shift ones from being used on I64 operands, as
they expect I32 input for most operations (eg. carry flag setting), and
expect I32 input for shift and boolean amounts. Most other helper
functions don't take Operands, throw on out of range values, and take
specific types of OpCode, so didn't need any asserts.
* Use ConstF rather than creating an operand.
(useful for pooling in future)
* Move exclusive load to helper, reference call flag rather than literal 1.
* Address LDj feedback (minus table flatten)
one final look before it's all gone. the world is so beautiful.
* Flatten OpCodeTable
oh no
* Address more table ordering
* Call Flag as int on A32
Co-authored-by: Natalie C. <cyuubiapps@gmail.com>
Co-authored-by: Thog <thog@protonmail.com>
420 lines
14 KiB
C#
420 lines
14 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using System;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Translation
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{
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static class RegisterUsage
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{
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private const long CallerSavedIntRegistersMask = 0x7fL << 9;
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private const long PStateNzcvFlagsMask = 0xfL << 60;
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private const long FpStateNzcvFlagsMask = 0xfL << 60;
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private const long CallerSavedVecRegistersMask = 0xffffL << 16;
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private const int RegsCount = 32;
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private const int RegsMask = RegsCount - 1;
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private struct RegisterMask : IEquatable<RegisterMask>
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{
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public long IntMask { get; set; }
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public long VecMask { get; set; }
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public RegisterMask(long intMask, long vecMask)
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{
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IntMask = intMask;
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VecMask = vecMask;
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}
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public static RegisterMask operator &(RegisterMask x, RegisterMask y)
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{
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return new RegisterMask(x.IntMask & y.IntMask, x.VecMask & y.VecMask);
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}
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public static RegisterMask operator |(RegisterMask x, RegisterMask y)
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{
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return new RegisterMask(x.IntMask | y.IntMask, x.VecMask | y.VecMask);
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}
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public static RegisterMask operator ~(RegisterMask x)
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{
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return new RegisterMask(~x.IntMask, ~x.VecMask);
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}
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public static bool operator ==(RegisterMask x, RegisterMask y)
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{
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return x.Equals(y);
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}
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public static bool operator !=(RegisterMask x, RegisterMask y)
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{
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return !x.Equals(y);
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}
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public override bool Equals(object obj)
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{
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return obj is RegisterMask regMask && Equals(regMask);
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}
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public bool Equals(RegisterMask other)
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{
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return IntMask == other.IntMask && VecMask == other.VecMask;
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}
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public override int GetHashCode()
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{
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return HashCode.Combine(IntMask, VecMask);
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}
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}
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public static void RunPass(ControlFlowGraph cfg, ExecutionMode mode, bool isCompleteFunction)
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{
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// Compute local register inputs and outputs used inside blocks.
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RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] localOutputs = new RegisterMask[cfg.Blocks.Count];
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for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext)
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{
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for (Node node = block.Operations.First; node != null; node = node.ListNext)
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{
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Operation operation = node as Operation;
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for (int srcIndex = 0; srcIndex < operation.SourcesCount; srcIndex++)
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{
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Operand source = operation.GetSource(srcIndex);
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if (source.Kind != OperandKind.Register)
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{
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continue;
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}
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Register register = source.GetRegister();
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localInputs[block.Index] |= GetMask(register) & ~localOutputs[block.Index];
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}
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if (operation.Destination != null && operation.Destination.Kind == OperandKind.Register)
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{
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localOutputs[block.Index] |= GetMask(operation.Destination.GetRegister());
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}
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}
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}
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// Compute global register inputs and outputs used across blocks.
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RegisterMask[] globalCmnOutputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Count];
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RegisterMask[] globalOutputs = new RegisterMask[cfg.Blocks.Count];
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bool modified;
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bool firstPass = true;
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do
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{
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modified = false;
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// Compute register outputs.
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for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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if (block.Predecessors.Count != 0 && !HasContextLoad(block))
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{
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BasicBlock predecessor = block.Predecessors[0];
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RegisterMask cmnOutputs = localOutputs[predecessor.Index] | globalCmnOutputs[predecessor.Index];
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RegisterMask outputs = globalOutputs[predecessor.Index];
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for (int pIndex = 1; pIndex < block.Predecessors.Count; pIndex++)
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{
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predecessor = block.Predecessors[pIndex];
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cmnOutputs &= localOutputs[predecessor.Index] | globalCmnOutputs[predecessor.Index];
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outputs |= globalOutputs[predecessor.Index];
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}
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globalInputs[block.Index] |= outputs & ~cmnOutputs;
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if (!firstPass)
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{
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cmnOutputs &= globalCmnOutputs[block.Index];
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}
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if (Exchange(globalCmnOutputs, block.Index, cmnOutputs))
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{
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modified = true;
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}
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outputs |= localOutputs[block.Index];
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if (Exchange(globalOutputs, block.Index, globalOutputs[block.Index] | outputs))
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{
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modified = true;
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}
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}
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else if (Exchange(globalOutputs, block.Index, localOutputs[block.Index]))
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{
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modified = true;
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}
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}
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// Compute register inputs.
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for (int index = 0; index < cfg.PostOrderBlocks.Length; index++)
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{
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BasicBlock block = cfg.PostOrderBlocks[index];
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RegisterMask inputs = localInputs[block.Index];
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if (block.Next != null)
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{
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inputs |= globalInputs[block.Next.Index];
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}
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if (block.Branch != null)
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{
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inputs |= globalInputs[block.Branch.Index];
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}
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inputs &= ~globalCmnOutputs[block.Index];
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if (Exchange(globalInputs, block.Index, globalInputs[block.Index] | inputs))
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{
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modified = true;
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}
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}
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firstPass = false;
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}
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while (modified);
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// Insert load and store context instructions where needed.
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for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext)
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{
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bool hasContextLoad = HasContextLoad(block);
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if (hasContextLoad)
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{
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block.Operations.Remove(block.Operations.First);
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}
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// The only block without any predecessor should be the entry block.
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// It always needs a context load as it is the first block to run.
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if (block.Predecessors.Count == 0 || hasContextLoad)
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{
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LoadLocals(block, globalInputs[block.Index].VecMask, RegisterType.Vector, mode);
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LoadLocals(block, globalInputs[block.Index].IntMask, RegisterType.Integer, mode);
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}
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bool hasContextStore = HasContextStore(block);
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if (hasContextStore)
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{
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block.Operations.Remove(block.Operations.Last);
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}
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if (EndsWithReturn(block) || hasContextStore)
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{
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StoreLocals(block, globalOutputs[block.Index].IntMask, RegisterType.Integer, mode, isCompleteFunction);
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StoreLocals(block, globalOutputs[block.Index].VecMask, RegisterType.Vector, mode, isCompleteFunction);
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}
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}
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}
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private static bool HasContextLoad(BasicBlock block)
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{
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return StartsWith(block, Instruction.LoadFromContext) && block.Operations.First.SourcesCount == 0;
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}
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private static bool HasContextStore(BasicBlock block)
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{
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return EndsWith(block, Instruction.StoreToContext) && block.GetLastOp().SourcesCount == 0;
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}
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private static bool StartsWith(BasicBlock block, Instruction inst)
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{
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if (block.Operations.Count == 0)
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{
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return false;
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}
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return block.Operations.First is Operation operation && operation.Instruction == inst;
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}
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private static bool EndsWith(BasicBlock block, Instruction inst)
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{
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if (block.Operations.Count == 0)
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{
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return false;
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}
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return block.Operations.Last is Operation operation && operation.Instruction == inst;
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}
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private static RegisterMask GetMask(Register register)
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{
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long intMask = 0;
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long vecMask = 0;
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switch (register.Type)
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{
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case RegisterType.Flag: intMask = (1L << RegsCount) << register.Index; break;
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case RegisterType.Integer: intMask = 1L << register.Index; break;
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case RegisterType.FpFlag: vecMask = (1L << RegsCount) << register.Index; break;
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case RegisterType.Vector: vecMask = 1L << register.Index; break;
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}
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return new RegisterMask(intMask, vecMask);
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}
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private static bool Exchange(RegisterMask[] masks, int blkIndex, RegisterMask value)
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{
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RegisterMask oldValue = masks[blkIndex];
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masks[blkIndex] = value;
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return oldValue != value;
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}
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private static void LoadLocals(BasicBlock block, long inputs, RegisterType baseType, ExecutionMode mode)
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{
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Operand arg0 = Local(OperandType.I64);
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for (int bit = 63; bit >= 0; bit--)
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{
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long mask = 1L << bit;
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if ((inputs & mask) == 0)
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{
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continue;
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}
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Operand dest = GetRegFromBit(bit, baseType, mode);
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long offset = NativeContext.GetRegisterOffset(dest.GetRegister());
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Operand addr = Local(OperandType.I64);
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Operation loadOp = new Operation(Instruction.Load, dest, addr);
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block.Operations.AddFirst(loadOp);
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Operation calcOffsOp = new Operation(Instruction.Add, addr, arg0, Const(offset));
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block.Operations.AddFirst(calcOffsOp);
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}
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Operation loadArg0 = new Operation(Instruction.LoadArgument, arg0, Const(0));
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block.Operations.AddFirst(loadArg0);
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}
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private static void StoreLocals(BasicBlock block, long outputs, RegisterType baseType, ExecutionMode mode, bool isCompleteFunction)
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{
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if (Optimizations.AssumeStrictAbiCompliance && isCompleteFunction)
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{
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if (baseType == RegisterType.Integer || baseType == RegisterType.Flag)
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{
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outputs = ClearCallerSavedIntRegs(outputs);
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}
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else /* if (baseType == RegisterType.Vector || baseType == RegisterType.FpFlag) */
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{
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outputs = ClearCallerSavedVecRegs(outputs);
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}
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}
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Operand arg0 = Local(OperandType.I64);
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Operation loadArg0 = new Operation(Instruction.LoadArgument, arg0, Const(0));
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block.Append(loadArg0);
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for (int bit = 0; bit < 64; bit++)
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{
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long mask = 1L << bit;
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if ((outputs & mask) == 0)
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{
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continue;
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}
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Operand source = GetRegFromBit(bit, baseType, mode);
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long offset = NativeContext.GetRegisterOffset(source.GetRegister());
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Operand addr = Local(OperandType.I64);
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Operation calcOffsOp = new Operation(Instruction.Add, addr, arg0, Const(offset));
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block.Append(calcOffsOp);
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Operation storeOp = new Operation(Instruction.Store, null, addr, source);
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block.Append(storeOp);
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}
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}
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private static Operand GetRegFromBit(int bit, RegisterType baseType, ExecutionMode mode)
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{
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if (bit < RegsCount)
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{
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return new Operand(bit, baseType, GetOperandType(baseType, mode));
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}
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else if (baseType == RegisterType.Integer)
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{
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return new Operand(bit & RegsMask, RegisterType.Flag, OperandType.I32);
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}
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else if (baseType == RegisterType.Vector)
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{
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return new Operand(bit & RegsMask, RegisterType.FpFlag, OperandType.I32);
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}
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else
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{
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throw new ArgumentOutOfRangeException(nameof(bit));
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}
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}
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private static OperandType GetOperandType(RegisterType type, ExecutionMode mode)
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{
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switch (type)
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{
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case RegisterType.Flag: return OperandType.I32;
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case RegisterType.FpFlag: return OperandType.I32;
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case RegisterType.Integer: return (mode == ExecutionMode.Aarch64) ? OperandType.I64 : OperandType.I32;
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case RegisterType.Vector: return OperandType.V128;
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}
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throw new ArgumentException($"Invalid register type \"{type}\".");
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}
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private static bool EndsWithReturn(BasicBlock block)
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{
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if (!(block.GetLastOp() is Operation operation))
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{
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return false;
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}
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return operation.Instruction == Instruction.Return;
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}
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private static long ClearCallerSavedIntRegs(long mask)
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{
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// TODO: ARM32 support.
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mask &= ~(CallerSavedIntRegistersMask | PStateNzcvFlagsMask);
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return mask;
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}
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private static long ClearCallerSavedVecRegs(long mask)
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{
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// TODO: ARM32 support.
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mask &= ~(CallerSavedVecRegistersMask | FpStateNzcvFlagsMask);
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return mask;
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}
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}
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} |