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https://github.com/Ryujinx/Ryujinx.git
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* WIP Range Tracking - Texture invalidation seems to have large problems - Buffer/Pool invalidation may have problems - Mirror memory tracking puts an additional `add` in compiled code, we likely just want to make HLE access slower if this is the final solution. - Native project is in the messiest possible location. - [HACK] JIT memory access always uses native "fast" path - [HACK] Trying some things with texture invalidation and views. It works :) Still a few hacks, messy things, slow things More work in progress stuff (also move to memory project) Quite a bit faster now. - Unmapping GPU VA and CPU VA will now correctly update write tracking regions, and invalidate textures for the former. - The Virtual range list is now non-overlapping like the physical one. - Fixed some bugs where regions could leak. - Introduced a weird bug that I still need to track down (consistent invalid buffer in MK8 ribbon road) Move some stuff. I think we'll eventually just put the dll and so for this in a nuget package. Fix rebase. [WIP] MultiRegionHandle variable size ranges - Avoid reprotecting regions that change often (needs some tweaking) - There's still a bug in buffers, somehow. - Might want different api for minimum granularity Fix rebase issue Commit everything needed for software only tracking. Remove native components. Remove more native stuff. Cleanup Use a separate window for the background context, update opentk. (fixes linux) Some experimental changes Should get things working up to scratch - still need to try some things with flush/modification and res scale. Include address with the region action. Initial work to make range tracking work Still a ton of bugs Fix some issues with the new stuff. * Fix texture flush instability There's still some weird behaviour, but it's much improved without this. (textures with cpu modified data were flushing over it) * Find the destination texture for Buffer->Texture full copy Greatly improves performance for nvdec videos (with range tracking) * Further improve texture tracking * Disable Memory Tracking for view parents This is a temporary approach to better match behaviour on master (where invalidations would be soaked up by views, rather than trigger twice) The assumption is that when views are created to a texture, they will cover all of its data anyways. Of course, this can easily be improved in future. * Introduce some tracking tests. WIP * Complete base tests. * Add more tests for multiregion, fix existing test. * Cleanup Part 1 * Remove unnecessary code from memory tracking * Fix some inconsistencies with 3D texture rule. * Add dispose tests. * Use a background thread for the background context. Rather than setting and unsetting a context as current, doing the work on a dedicated thread with signals seems to be a bit faster. Also nerf the multithreading test a bit. * Copy to texture with matching alignment This extends the copy to work for some videos with unusual size, such as tutorial videos in SMO. It will only occur if the destination texture already exists at XCount size. * Track reads for buffer copies. Synchronize new buffers before copying overlaps. * Remove old texture flushing mechanisms. Range tracking all the way, baby. * Wake the background thread when disposing. Avoids a deadlock when games are closed. * Address Feedback 1 * Separate TextureCopy instance for background thread Also `BackgroundContextWorker.InBackground` for a more sensible idenfifier for if we're in a background thread. * Add missing XML docs. * Address Feedback * Maybe I should start drinking coffee. * Some more feedback. * Remove flush warning, Refocus window after making background context
408 lines
14 KiB
C#
408 lines
14 KiB
C#
using Ryujinx.Cpu;
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using System;
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using System.Runtime.CompilerServices;
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using System.Runtime.InteropServices;
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namespace Ryujinx.Graphics.Gpu.Memory
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{
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/// <summary>
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/// GPU memory manager.
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/// </summary>
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public class MemoryManager
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{
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private const ulong AddressSpaceSize = 1UL << 40;
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public const ulong BadAddress = ulong.MaxValue;
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private const int PtLvl0Bits = 14;
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private const int PtLvl1Bits = 14;
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public const int PtPageBits = 12;
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private const ulong PtLvl0Size = 1UL << PtLvl0Bits;
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private const ulong PtLvl1Size = 1UL << PtLvl1Bits;
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public const ulong PageSize = 1UL << PtPageBits;
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private const ulong PtLvl0Mask = PtLvl0Size - 1;
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private const ulong PtLvl1Mask = PtLvl1Size - 1;
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public const ulong PageMask = PageSize - 1;
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private const int PtLvl0Bit = PtPageBits + PtLvl1Bits;
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private const int PtLvl1Bit = PtPageBits;
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private const ulong PteUnmapped = 0xffffffff_ffffffff;
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private const ulong PteReserved = 0xffffffff_fffffffe;
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private readonly ulong[][] _pageTable;
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public event EventHandler<UnmapEventArgs> MemoryUnmapped;
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private GpuContext _context;
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/// <summary>
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/// Creates a new instance of the GPU memory manager.
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/// </summary>
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public MemoryManager(GpuContext context)
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{
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_context = context;
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_pageTable = new ulong[PtLvl0Size][];
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}
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/// <summary>
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/// Reads data from GPU mapped memory.
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/// </summary>
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/// <typeparam name="T">Type of the data</typeparam>
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/// <param name="gpuVa">GPU virtual address where the data is located</param>
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/// <returns>The data at the specified memory location</returns>
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public T Read<T>(ulong gpuVa) where T : unmanaged
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{
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ulong processVa = Translate(gpuVa);
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return MemoryMarshal.Cast<byte, T>(_context.PhysicalMemory.GetSpan(processVa, Unsafe.SizeOf<T>()))[0];
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}
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/// <summary>
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/// Gets a read-only span of data from GPU mapped memory.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address where the data is located</param>
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/// <param name="size">Size of the data</param>
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/// <returns>The span of the data at the specified memory location</returns>
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public ReadOnlySpan<byte> GetSpan(ulong gpuVa, int size)
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{
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ulong processVa = Translate(gpuVa);
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return _context.PhysicalMemory.GetSpan(processVa, size);
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}
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/// <summary>
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/// Gets a writable region from GPU mapped memory.
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/// </summary>
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/// <param name="address">Start address of the range</param>
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/// <param name="size">Size in bytes to be range</param>
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/// <returns>A writable region with the data at the specified memory location</returns>
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public WritableRegion GetWritableRegion(ulong gpuVa, int size)
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{
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ulong processVa = Translate(gpuVa);
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return _context.PhysicalMemory.GetWritableRegion(processVa, size);
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}
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/// <summary>
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/// Writes data to GPU mapped memory.
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/// </summary>
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/// <typeparam name="T">Type of the data</typeparam>
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/// <param name="gpuVa">GPU virtual address to write the value into</param>
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/// <param name="value">The value to be written</param>
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public void Write<T>(ulong gpuVa, T value) where T : unmanaged
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{
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ulong processVa = Translate(gpuVa);
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_context.PhysicalMemory.Write(processVa, MemoryMarshal.Cast<T, byte>(MemoryMarshal.CreateSpan(ref value, 1)));
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}
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/// <summary>
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/// Writes data to GPU mapped memory.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address to write the data into</param>
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/// <param name="data">The data to be written</param>
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public void Write(ulong gpuVa, ReadOnlySpan<byte> data)
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{
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ulong processVa = Translate(gpuVa);
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_context.PhysicalMemory.Write(processVa, data);
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}
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/// <summary>
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/// Maps a given range of pages to the specified CPU virtual address.
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/// </summary>
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/// <remarks>
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/// All addresses and sizes must be page aligned.
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/// </remarks>
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/// <param name="pa">CPU virtual address to map into</param>
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/// <param name="va">GPU virtual address to be mapped</param>
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/// <param name="size">Size in bytes of the mapping</param>
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/// <returns>GPU virtual address of the mapping</returns>
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public ulong Map(ulong pa, ulong va, ulong size)
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{
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lock (_pageTable)
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{
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MemoryUnmapped?.Invoke(this, new UnmapEventArgs(va, size));
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, pa + offset);
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}
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}
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return va;
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}
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/// <summary>
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/// Maps a given range of pages to an allocated GPU virtual address.
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/// The memory is automatically allocated by the memory manager.
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/// </summary>
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/// <param name="pa">CPU virtual address to map into</param>
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/// <param name="size">Size in bytes of the mapping</param>
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/// <param name="alignment">Required alignment of the GPU virtual address in bytes</param>
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/// <returns>GPU virtual address where the range was mapped, or an all ones mask in case of failure</returns>
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public ulong MapAllocate(ulong pa, ulong size, ulong alignment)
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{
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lock (_pageTable)
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{
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ulong va = GetFreePosition(size, alignment);
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if (va != PteUnmapped)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, pa + offset);
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}
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}
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return va;
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}
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}
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/// <summary>
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/// Maps a given range of pages to an allocated GPU virtual address.
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/// The memory is automatically allocated by the memory manager.
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/// This also ensures that the mapping is always done in the first 4GB of GPU address space.
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/// </summary>
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/// <param name="pa">CPU virtual address to map into</param>
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/// <param name="size">Size in bytes of the mapping</param>
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/// <returns>GPU virtual address where the range was mapped, or an all ones mask in case of failure</returns>
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public ulong MapLow(ulong pa, ulong size)
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{
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lock (_pageTable)
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{
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ulong va = GetFreePosition(size, 1, PageSize);
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if (va != PteUnmapped && va <= uint.MaxValue && (va + size) <= uint.MaxValue)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, pa + offset);
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}
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}
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else
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{
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va = PteUnmapped;
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}
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return va;
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}
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}
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/// <summary>
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/// Reserves memory at a fixed GPU memory location.
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/// This prevents the reserved region from being used for memory allocation for map.
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/// </summary>
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/// <param name="va">GPU virtual address to reserve</param>
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/// <param name="size">Size in bytes of the reservation</param>
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/// <returns>GPU virtual address of the reservation, or an all ones mask in case of failure</returns>
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public ulong ReserveFixed(ulong va, ulong size)
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{
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lock (_pageTable)
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{
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MemoryUnmapped?.Invoke(this, new UnmapEventArgs(va, size));
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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if (IsPageInUse(va + offset))
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{
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return PteUnmapped;
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}
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}
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, PteReserved);
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}
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}
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return va;
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}
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/// <summary>
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/// Reserves memory at any GPU memory location.
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/// </summary>
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/// <param name="size">Size in bytes of the reservation</param>
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/// <param name="alignment">Reservation address alignment in bytes</param>
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/// <returns>GPU virtual address of the reservation, or an all ones mask in case of failure</returns>
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public ulong Reserve(ulong size, ulong alignment)
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{
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lock (_pageTable)
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{
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ulong address = GetFreePosition(size, alignment);
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if (address != PteUnmapped)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(address + offset, PteReserved);
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}
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}
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return address;
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}
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}
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/// <summary>
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/// Frees memory that was previously allocated by a map or reserved.
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/// </summary>
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/// <param name="va">GPU virtual address to free</param>
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/// <param name="size">Size in bytes of the region being freed</param>
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public void Free(ulong va, ulong size)
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{
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lock (_pageTable)
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{
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// Event handlers are not expected to be thread safe.
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MemoryUnmapped?.Invoke(this, new UnmapEventArgs(va, size));
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, PteUnmapped);
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}
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}
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}
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/// <summary>
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/// Gets the address of an unused (free) region of the specified size.
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/// </summary>
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/// <param name="size">Size of the region in bytes</param>
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/// <param name="alignment">Required alignment of the region address in bytes</param>
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/// <param name="start">Start address of the search on the address space</param>
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/// <returns>GPU virtual address of the allocation, or an all ones mask in case of failure</returns>
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private ulong GetFreePosition(ulong size, ulong alignment = 1, ulong start = 1UL << 32)
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{
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// Note: Address 0 is not considered valid by the driver,
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// when 0 is returned it's considered a mapping error.
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ulong address = start;
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ulong freeSize = 0;
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if (alignment == 0)
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{
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alignment = 1;
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}
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alignment = (alignment + PageMask) & ~PageMask;
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while (address + freeSize < AddressSpaceSize)
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{
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if (!IsPageInUse(address + freeSize))
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{
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freeSize += PageSize;
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if (freeSize >= size)
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{
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return address;
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}
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}
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else
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{
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address += freeSize + PageSize;
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freeSize = 0;
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ulong remainder = address % alignment;
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if (remainder != 0)
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{
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address = (address - remainder) + alignment;
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}
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}
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}
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return PteUnmapped;
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}
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/// <summary>
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/// Checks if a given page is mapped.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address of the page to check</param>
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/// <returns>True if the page is mapped, false otherwise</returns>
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public bool IsMapped(ulong gpuVa)
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{
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return Translate(gpuVa) != PteUnmapped;
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}
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/// <summary>
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/// Translates a GPU virtual address to a CPU virtual address.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address to be translated</param>
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/// <returns>CPU virtual address</returns>
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public ulong Translate(ulong gpuVa)
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{
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ulong baseAddress = GetPte(gpuVa);
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if (baseAddress == PteUnmapped || baseAddress == PteReserved)
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{
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return PteUnmapped;
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}
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return baseAddress + (gpuVa & PageMask);
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}
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/// <summary>
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/// Checks if a given memory page is mapped or reserved.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address of the page</param>
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/// <returns>True if the page is mapped or reserved, false otherwise</returns>
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private bool IsPageInUse(ulong gpuVa)
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{
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if (gpuVa >> PtLvl0Bits + PtLvl1Bits + PtPageBits != 0)
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{
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return false;
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}
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ulong l0 = (gpuVa >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (gpuVa >> PtLvl1Bit) & PtLvl1Mask;
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if (_pageTable[l0] == null)
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{
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return false;
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}
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return _pageTable[l0][l1] != PteUnmapped;
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}
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/// <summary>
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/// Gets the Page Table entry for a given GPU virtual address.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address</param>
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/// <returns>Page table entry (CPU virtual address)</returns>
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private ulong GetPte(ulong gpuVa)
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{
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ulong l0 = (gpuVa >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (gpuVa >> PtLvl1Bit) & PtLvl1Mask;
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if (_pageTable[l0] == null)
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{
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return PteUnmapped;
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}
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return _pageTable[l0][l1];
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}
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/// <summary>
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/// Sets a Page Table entry at a given GPU virtual address.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address</param>
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/// <param name="pte">Page table entry (CPU virtual address)</param>
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private void SetPte(ulong gpuVa, ulong pte)
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{
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ulong l0 = (gpuVa >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (gpuVa >> PtLvl1Bit) & PtLvl1Mask;
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if (_pageTable[l0] == null)
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{
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_pageTable[l0] = new ulong[PtLvl1Size];
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for (ulong index = 0; index < PtLvl1Size; index++)
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{
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_pageTable[l0][index] = PteUnmapped;
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}
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}
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_pageTable[l0][l1] = pte;
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}
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}
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} |