b956bbc32c
* Update AOpCodeTable.cs * Update AInstEmitSystem.cs * Update AInstEmitSimdHash.cs * Update ASoftFallback.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
138 lines
4.5 KiB
C#
138 lines
4.5 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Hint(AILEmitterCtx Context)
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{
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//Execute as no-op.
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}
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public static void Isb(AILEmitterCtx Context)
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{
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//Execute as no-op.
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}
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public static void Mrs(AILEmitterCtx Context)
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{
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AOpCodeSystem Op = (AOpCodeSystem)Context.CurrOp;
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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string PropName;
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switch (GetPackedId(Op))
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{
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case 0b11_011_0000_0000_001: PropName = nameof(AThreadState.CtrEl0); break;
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case 0b11_011_0000_0000_111: PropName = nameof(AThreadState.DczidEl0); break;
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case 0b11_011_0100_0100_000: PropName = nameof(AThreadState.Fpcr); break;
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case 0b11_011_0100_0100_001: PropName = nameof(AThreadState.Fpsr); break;
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case 0b11_011_1101_0000_010: PropName = nameof(AThreadState.TpidrEl0); break;
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case 0b11_011_1101_0000_011: PropName = nameof(AThreadState.Tpidr); break;
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case 0b11_011_1110_0000_000: PropName = nameof(AThreadState.CntfrqEl0); break;
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case 0b11_011_1110_0000_001: PropName = nameof(AThreadState.CntpctEl0); break;
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default: throw new NotImplementedException($"Unknown MRS at {Op.Position:x16}");
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}
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Context.EmitCallPropGet(typeof(AThreadState), PropName);
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PropertyInfo PropInfo = typeof(AThreadState).GetProperty(PropName);
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if (PropInfo.PropertyType != typeof(long) &&
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PropInfo.PropertyType != typeof(ulong))
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{
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Context.Emit(OpCodes.Conv_U8);
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}
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Context.EmitStintzr(Op.Rt);
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}
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public static void Msr(AILEmitterCtx Context)
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{
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AOpCodeSystem Op = (AOpCodeSystem)Context.CurrOp;
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitLdintzr(Op.Rt);
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string PropName;
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switch (GetPackedId(Op))
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{
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case 0b11_011_0100_0100_000: PropName = nameof(AThreadState.Fpcr); break;
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case 0b11_011_0100_0100_001: PropName = nameof(AThreadState.Fpsr); break;
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case 0b11_011_1101_0000_010: PropName = nameof(AThreadState.TpidrEl0); break;
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default: throw new NotImplementedException($"Unknown MSR at {Op.Position:x16}");
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}
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PropertyInfo PropInfo = typeof(AThreadState).GetProperty(PropName);
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if (PropInfo.PropertyType != typeof(long) &&
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PropInfo.PropertyType != typeof(ulong))
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{
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Context.Emit(OpCodes.Conv_U4);
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}
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Context.EmitCallPropSet(typeof(AThreadState), PropName);
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}
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public static void Nop(AILEmitterCtx Context)
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{
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//Do nothing.
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}
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public static void Sys(AILEmitterCtx Context)
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{
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//This instruction is used to do some operations on the CPU like cache invalidation,
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//address translation and the like.
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//We treat it as no-op here since we don't have any cache being emulated anyway.
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AOpCodeSystem Op = (AOpCodeSystem)Context.CurrOp;
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switch (GetPackedId(Op))
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{
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case 0b11_011_0111_0100_001:
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{
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//DC ZVA
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for (int Offs = 0; Offs < (4 << AThreadState.DczSizeLog2); Offs += 8)
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{
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Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
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Context.EmitLdintzr(Op.Rt);
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Context.EmitLdc_I(Offs);
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Context.Emit(OpCodes.Add);
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Context.EmitLdc_I8(0);
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AInstEmitMemoryHelper.EmitWriteCall(Context, 3);
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}
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break;
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}
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//No-op
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case 0b11_011_0111_1110_001: //DC CIVAC
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break;
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}
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}
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private static int GetPackedId(AOpCodeSystem Op)
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{
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int Id;
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Id = Op.Op2 << 0;
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Id |= Op.CRm << 3;
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Id |= Op.CRn << 7;
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Id |= Op.Op1 << 11;
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Id |= Op.Op0 << 14;
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return Id;
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}
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}
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}
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