8b44eb1c98
* Use DeviceState for compute and i2m * Migrate 2D class, more comments * Migrate DMA copy engine * Remove now unused code * Replace GpuState by GpuAccessorState on GpuAcessor, since compute no longer has a GpuState * More comments * Add logging (disabled) * Add back i2m on 3D engine
233 lines
6.9 KiB
C#
233 lines
6.9 KiB
C#
// This file was auto-generated from NVIDIA official Maxwell definitions.
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using Ryujinx.Common.Memory;
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namespace Ryujinx.Graphics.Gpu.Engine.GPFifo
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{
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/// <summary>
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/// Semaphore operation.
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/// </summary>
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enum SemaphoredOperation
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{
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Acquire = 1,
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Release = 2,
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AcqGeq = 4,
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AcqAnd = 8,
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Reduction = 16
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}
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/// <summary>
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/// Semaphore acquire switch enable.
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/// </summary>
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enum SemaphoredAcquireSwitch
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{
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Disabled = 0,
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Enabled = 1
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}
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/// <summary>
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/// Semaphore release interrupt wait enable.
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/// </summary>
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enum SemaphoredReleaseWfi
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{
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En = 0,
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Dis = 1
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}
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/// <summary>
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/// Semaphore release structure size.
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/// </summary>
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enum SemaphoredReleaseSize
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{
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SixteenBytes = 0,
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FourBytes = 1
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}
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/// <summary>
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/// Semaphore reduction operation.
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/// </summary>
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enum SemaphoredReduction
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{
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Min = 0,
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Max = 1,
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Xor = 2,
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And = 3,
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Or = 4,
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Add = 5,
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Inc = 6,
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Dec = 7
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}
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/// <summary>
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/// Semaphore format.
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/// </summary>
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enum SemaphoredFormat
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{
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Signed = 0,
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Unsigned = 1
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}
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/// <summary>
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/// Memory Translation Lookaside Buffer Page Directory Buffer invalidation.
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/// </summary>
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enum MemOpCTlbInvalidatePdb
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{
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One = 0,
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All = 1
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}
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/// <summary>
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/// Memory Translation Lookaside Buffer GPC invalidation enable.
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/// </summary>
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enum MemOpCTlbInvalidateGpc
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{
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Enable = 0,
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Disable = 1
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}
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/// <summary>
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/// Memory Translation Lookaside Buffer invalidation target.
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/// </summary>
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enum MemOpCTlbInvalidateTarget
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{
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VidMem = 0,
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SysMemCoherent = 2,
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SysMemNoncoherent = 3
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}
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/// <summary>
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/// Memory operation.
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/// </summary>
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enum MemOpDOperation
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{
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Membar = 5,
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MmuTlbInvalidate = 9,
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L2PeermemInvalidate = 13,
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L2SysmemInvalidate = 14,
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L2CleanComptags = 15,
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L2FlushDirty = 16
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}
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/// <summary>
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/// Syncpoint operation.
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/// </summary>
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enum SyncpointbOperation
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{
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Wait = 0,
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Incr = 1
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}
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/// <summary>
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/// Syncpoint wait switch enable.
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/// </summary>
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enum SyncpointbWaitSwitch
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{
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Dis = 0,
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En = 1
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}
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/// <summary>
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/// Wait for interrupt scope.
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/// </summary>
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enum WfiScope
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{
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CurrentScgType = 0,
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All = 1
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}
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/// <summary>
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/// Yield operation.
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/// </summary>
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enum YieldOp
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{
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Nop = 0,
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PbdmaTimeslice = 1,
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RunlistTimeslice = 2,
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Tsg = 3
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}
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/// <summary>
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/// General Purpose FIFO class state.
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/// </summary>
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struct GPFifoClassState
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{
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#pragma warning disable CS0649
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public uint SetObject;
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public int SetObjectNvclass => (int)((SetObject >> 0) & 0xFFFF);
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public int SetObjectEngine => (int)((SetObject >> 16) & 0x1F);
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public uint Illegal;
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public int IllegalHandle => (int)(Illegal);
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public uint Nop;
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public int NopHandle => (int)(Nop);
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public uint Reserved0C;
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public uint Semaphorea;
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public int SemaphoreaOffsetUpper => (int)((Semaphorea >> 0) & 0xFF);
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public uint Semaphoreb;
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public int SemaphorebOffsetLower => (int)((Semaphoreb >> 2) & 0x3FFFFFFF);
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public uint Semaphorec;
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public int SemaphorecPayload => (int)(Semaphorec);
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public uint Semaphored;
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public SemaphoredOperation SemaphoredOperation => (SemaphoredOperation)((Semaphored >> 0) & 0x1F);
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public SemaphoredAcquireSwitch SemaphoredAcquireSwitch => (SemaphoredAcquireSwitch)((Semaphored >> 12) & 0x1);
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public SemaphoredReleaseWfi SemaphoredReleaseWfi => (SemaphoredReleaseWfi)((Semaphored >> 20) & 0x1);
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public SemaphoredReleaseSize SemaphoredReleaseSize => (SemaphoredReleaseSize)((Semaphored >> 24) & 0x1);
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public SemaphoredReduction SemaphoredReduction => (SemaphoredReduction)((Semaphored >> 27) & 0xF);
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public SemaphoredFormat SemaphoredFormat => (SemaphoredFormat)((Semaphored >> 31) & 0x1);
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public uint NonStallInterrupt;
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public int NonStallInterruptHandle => (int)(NonStallInterrupt);
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public uint FbFlush;
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public int FbFlushHandle => (int)(FbFlush);
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public uint Reserved28;
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public uint Reserved2C;
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public uint MemOpC;
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public int MemOpCOperandLow => (int)((MemOpC >> 2) & 0x3FFFFFFF);
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public MemOpCTlbInvalidatePdb MemOpCTlbInvalidatePdb => (MemOpCTlbInvalidatePdb)((MemOpC >> 0) & 0x1);
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public MemOpCTlbInvalidateGpc MemOpCTlbInvalidateGpc => (MemOpCTlbInvalidateGpc)((MemOpC >> 1) & 0x1);
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public MemOpCTlbInvalidateTarget MemOpCTlbInvalidateTarget => (MemOpCTlbInvalidateTarget)((MemOpC >> 10) & 0x3);
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public int MemOpCTlbInvalidateAddrLo => (int)((MemOpC >> 12) & 0xFFFFF);
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public uint MemOpD;
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public int MemOpDOperandHigh => (int)((MemOpD >> 0) & 0xFF);
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public MemOpDOperation MemOpDOperation => (MemOpDOperation)((MemOpD >> 27) & 0x1F);
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public int MemOpDTlbInvalidateAddrHi => (int)((MemOpD >> 0) & 0xFF);
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public uint Reserved38;
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public uint Reserved3C;
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public uint Reserved40;
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public uint Reserved44;
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public uint Reserved48;
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public uint Reserved4C;
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public uint SetReference;
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public int SetReferenceCount => (int)(SetReference);
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public uint Reserved54;
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public uint Reserved58;
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public uint Reserved5C;
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public uint Reserved60;
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public uint Reserved64;
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public uint Reserved68;
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public uint Reserved6C;
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public uint Syncpointa;
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public int SyncpointaPayload => (int)(Syncpointa);
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public uint Syncpointb;
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public SyncpointbOperation SyncpointbOperation => (SyncpointbOperation)((Syncpointb >> 0) & 0x1);
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public SyncpointbWaitSwitch SyncpointbWaitSwitch => (SyncpointbWaitSwitch)((Syncpointb >> 4) & 0x1);
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public int SyncpointbSyncptIndex => (int)((Syncpointb >> 8) & 0xFFF);
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public uint Wfi;
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public WfiScope WfiScope => (WfiScope)((Wfi >> 0) & 0x1);
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public uint CrcCheck;
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public int CrcCheckValue => (int)(CrcCheck);
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public uint Yield;
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public YieldOp YieldOp => (YieldOp)((Yield >> 0) & 0x3);
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// TODO: Eventually move this to per-engine state.
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public Array31<uint> Reserved84;
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public uint NoOperation;
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public uint SetNotifyA;
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public uint SetNotifyB;
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public uint Notify;
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public uint WaitForIdle;
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public uint LoadMmeInstructionRamPointer;
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public uint LoadMmeInstructionRam;
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public uint LoadMmeStartAddressRamPointer;
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public uint LoadMmeStartAddressRam;
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public uint SetMmeShadowRamControl;
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#pragma warning restore CS0649
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}
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}
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