mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-08-17 22:28:43 +02:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
459 lines
7.3 KiB
C#
459 lines
7.3 KiB
C#
namespace ARMeilleure.Instructions
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{
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enum InstName
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{
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// Base (AArch64)
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Adc,
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Adcs,
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Add,
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Adds,
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Adr,
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Adrp,
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And,
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Ands,
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Asrv,
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B,
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B_Cond,
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Bfm,
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Bic,
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Bics,
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Bl,
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Blr,
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Br,
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Brk,
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Cbnz,
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Cbz,
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Ccmn,
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Ccmp,
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Clrex,
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Cls,
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Clz,
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Crc32b,
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Crc32h,
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Crc32w,
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Crc32x,
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Crc32cb,
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Crc32ch,
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Crc32cw,
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Crc32cx,
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Csel,
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Csinc,
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Csinv,
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Csneg,
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Dmb,
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Dsb,
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Eon,
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Eor,
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Extr,
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Hint,
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Isb,
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Ldar,
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Ldaxp,
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Ldaxr,
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Ldp,
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Ldr,
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Ldr_Literal,
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Ldrs,
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Ldxr,
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Ldxp,
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Lslv,
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Lsrv,
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Madd,
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Movk,
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Movn,
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Movz,
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Mrs,
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Msr,
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Msub,
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Nop,
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Orn,
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Orr,
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Pfrm,
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Rbit,
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Ret,
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Rev16,
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Rev32,
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Rev64,
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Rorv,
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Sbc,
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Sbcs,
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Sbfm,
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Sdiv,
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Smaddl,
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Smsubl,
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Smulh,
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Stlr,
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Stlxp,
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Stlxr,
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Stp,
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Str,
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Stxp,
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Stxr,
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Sub,
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Subs,
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Svc,
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Sys,
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Tbnz,
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Tbz,
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Ubfm,
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Udiv,
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Umaddl,
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Umsubl,
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Umulh,
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Und,
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// FP & SIMD (AArch64)
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Abs_S,
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Abs_V,
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Add_S,
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Add_V,
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Addhn_V,
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Addp_S,
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Addp_V,
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Addv_V,
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Aesd_V,
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Aese_V,
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Aesimc_V,
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Aesmc_V,
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And_V,
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Bic_V,
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Bic_Vi,
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Bif_V,
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Bit_V,
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Bsl_V,
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Cls_V,
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Clz_V,
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Cmeq_S,
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Cmeq_V,
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Cmge_S,
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Cmge_V,
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Cmgt_S,
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Cmgt_V,
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Cmhi_S,
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Cmhi_V,
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Cmhs_S,
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Cmhs_V,
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Cmle_S,
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Cmle_V,
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Cmlt_S,
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Cmlt_V,
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Cmtst_S,
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Cmtst_V,
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Cnt_V,
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Dup_Gp,
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Dup_S,
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Dup_V,
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Eor_V,
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Ext_V,
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Fabd_S,
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Fabd_V,
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Fabs_S,
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Fabs_V,
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Fadd_S,
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Fadd_V,
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Faddp_S,
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Faddp_V,
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Fccmp_S,
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Fccmpe_S,
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Fcmeq_S,
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Fcmeq_V,
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Fcmge_S,
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Fcmge_V,
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Fcmgt_S,
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Fcmgt_V,
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Fcmle_S,
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Fcmle_V,
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Fcmlt_S,
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Fcmlt_V,
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Fcmp_S,
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Fcmpe_S,
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Fcsel_S,
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Fcvt_S,
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Fcvtas_Gp,
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Fcvtau_Gp,
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Fcvtl_V,
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Fcvtms_Gp,
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Fcvtmu_Gp,
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Fcvtn_V,
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Fcvtns_S,
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Fcvtns_V,
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Fcvtnu_S,
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Fcvtnu_V,
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Fcvtps_Gp,
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Fcvtpu_Gp,
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Fcvtzs_Gp,
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Fcvtzs_Gp_Fixed,
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Fcvtzs_S,
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Fcvtzs_V,
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Fcvtzs_V_Fixed,
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Fcvtzu_Gp,
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Fcvtzu_Gp_Fixed,
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Fcvtzu_S,
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Fcvtzu_V,
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Fcvtzu_V_Fixed,
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Fdiv_S,
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Fdiv_V,
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Fmadd_S,
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Fmax_S,
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Fmax_V,
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Fmaxnm_S,
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Fmaxnm_V,
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Fmaxp_V,
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Fmin_S,
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Fmin_V,
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Fminnm_S,
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Fminnm_V,
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Fminp_V,
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Fmla_Se,
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Fmla_V,
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Fmla_Ve,
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Fmls_Se,
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Fmls_V,
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Fmls_Ve,
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Fmov_S,
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Fmov_Si,
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Fmov_Vi,
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Fmov_Ftoi,
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Fmov_Itof,
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Fmov_Ftoi1,
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Fmov_Itof1,
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Fmsub_S,
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Fmul_S,
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Fmul_Se,
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Fmul_V,
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Fmul_Ve,
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Fmulx_S,
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Fmulx_Se,
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Fmulx_V,
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Fmulx_Ve,
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Fneg_S,
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Fneg_V,
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Fnmadd_S,
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Fnmsub_S,
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Fnmul_S,
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Frecpe_S,
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Frecpe_V,
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Frecps_S,
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Frecps_V,
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Frecpx_S,
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Frinta_S,
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Frinta_V,
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Frinti_S,
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Frinti_V,
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Frintm_S,
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Frintm_V,
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Frintn_S,
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Frintn_V,
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Frintp_S,
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Frintp_V,
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Frintx_S,
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Frintx_V,
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Frintz_S,
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Frintz_V,
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Frsqrte_S,
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Frsqrte_V,
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Frsqrts_S,
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Frsqrts_V,
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Fsqrt_S,
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Fsqrt_V,
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Fsub_S,
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Fsub_V,
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Ins_Gp,
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Ins_V,
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Ld__Vms,
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Ld__Vss,
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Mla_V,
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Mla_Ve,
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Mls_V,
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Mls_Ve,
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Movi_V,
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Mul_V,
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Mul_Ve,
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Mvni_V,
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Neg_S,
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Neg_V,
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Not_V,
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Orn_V,
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Orr_V,
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Orr_Vi,
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Raddhn_V,
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Rbit_V,
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Rev16_V,
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Rev32_V,
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Rev64_V,
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Rshrn_V,
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Rsubhn_V,
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Saba_V,
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Sabal_V,
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Sabd_V,
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Sabdl_V,
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Sadalp_V,
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Saddl_V,
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Saddlp_V,
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Saddlv_V,
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Saddw_V,
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Scvtf_Gp,
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Scvtf_Gp_Fixed,
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Scvtf_S,
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Scvtf_V,
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Scvtf_V_Fixed,
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Sha1c_V,
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Sha1h_V,
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Sha1m_V,
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Sha1p_V,
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Sha1su0_V,
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Sha1su1_V,
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Sha256h_V,
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Sha256h2_V,
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Sha256su0_V,
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Sha256su1_V,
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Shadd_V,
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Shl_S,
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Shl_V,
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Shll_V,
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Shrn_V,
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Shsub_V,
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Sli_V,
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Smax_V,
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Smaxp_V,
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Smaxv_V,
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Smin_V,
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Sminp_V,
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Sminv_V,
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Smlal_V,
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Smlal_Ve,
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Smlsl_V,
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Smlsl_Ve,
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Smov_S,
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Smull_V,
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Smull_Ve,
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Sqabs_S,
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Sqabs_V,
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Sqadd_S,
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Sqadd_V,
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Sqdmulh_S,
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Sqdmulh_V,
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Sqneg_S,
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Sqneg_V,
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Sqrdmulh_S,
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Sqrdmulh_V,
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Sqrshl_V,
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Sqrshrn_S,
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Sqrshrn_V,
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Sqrshrun_S,
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Sqrshrun_V,
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Sqshl_V,
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Sqshrn_S,
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Sqshrn_V,
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Sqshrun_S,
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Sqshrun_V,
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Sqsub_S,
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Sqsub_V,
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Sqxtn_S,
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Sqxtn_V,
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Sqxtun_S,
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Sqxtun_V,
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Srhadd_V,
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Srshl_V,
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Srshr_S,
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Srshr_V,
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Srsra_S,
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Srsra_V,
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Sshl_V,
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Sshll_V,
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Sshr_S,
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Sshr_V,
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Ssra_S,
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Ssra_V,
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Ssubl_V,
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Ssubw_V,
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St__Vms,
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St__Vss,
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Sub_S,
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Sub_V,
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Subhn_V,
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Suqadd_S,
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Suqadd_V,
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Tbl_V,
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Trn1_V,
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Trn2_V,
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Uaba_V,
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Uabal_V,
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Uabd_V,
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Uabdl_V,
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Uadalp_V,
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Uaddl_V,
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Uaddlp_V,
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Uaddlv_V,
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Uaddw_V,
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Ucvtf_Gp,
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Ucvtf_Gp_Fixed,
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Ucvtf_S,
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Ucvtf_V,
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Ucvtf_V_Fixed,
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Uhadd_V,
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Uhsub_V,
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Umax_V,
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Umaxp_V,
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Umaxv_V,
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Umin_V,
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Uminp_V,
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Uminv_V,
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Umlal_V,
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Umlal_Ve,
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Umlsl_V,
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Umlsl_Ve,
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Umov_S,
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Umull_V,
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Umull_Ve,
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Uqadd_S,
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Uqadd_V,
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Uqrshl_V,
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Uqrshrn_S,
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Uqrshrn_V,
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Uqshl_V,
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Uqshrn_S,
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Uqshrn_V,
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Uqsub_S,
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Uqsub_V,
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Uqxtn_S,
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Uqxtn_V,
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Urhadd_V,
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Urshl_V,
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Urshr_S,
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Urshr_V,
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Ursra_S,
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Ursra_V,
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Ushl_V,
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Ushll_V,
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Ushr_S,
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Ushr_V,
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Usqadd_S,
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Usqadd_V,
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Usra_S,
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Usra_V,
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Usubl_V,
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Usubw_V,
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Uzp1_V,
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Uzp2_V,
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Xtn_V,
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Zip1_V,
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Zip2_V,
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// Base (AArch32)
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Blx,
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Bx,
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Cmp,
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Ldm,
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Ldrb,
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Ldrd,
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Ldrh,
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Ldrsb,
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Ldrsh,
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Mov,
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Stm,
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Strb,
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Strd,
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Strh
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}
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} |