02a6fdcd13
* Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update CpuTestAlu.cs * Update CpuTestAluImm.cs * Update CpuTestAluRs.cs * Update CpuTestAluRx.cs * Update CpuTestBfm.cs * Update CpuTestCcmpImm.cs * Update CpuTestCcmpReg.cs * Update CpuTestCsel.cs * Update CpuTestMov.cs * Update CpuTestMul.cs * Update Ryujinx.Tests.csproj * Update Ryujinx.csproj * Update Luea.csproj * Update Ryujinx.ShaderTools.csproj * Address PR feedback (further tested). * Address PR feedback.
331 lines
12 KiB
C#
331 lines
12 KiB
C#
//#define Alu
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Alu"), Ignore("Tested: second half of 2018.")]
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public sealed class CpuTestAlu : CpuTest
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{
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#if Alu
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[SetUp]
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public void SetupTester()
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{
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AArch64.TakeReset(false);
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}
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[Test, Description("CLS <Xd>, <Xn>")]
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public void Cls_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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uint Opcode = 0xDAC01400; // CLS X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("CLS <Wd>, <Wn>")]
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public void Cls_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
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{
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uint Opcode = 0x5AC01400; // CLS W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("CLZ <Xd>, <Xn>")]
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public void Clz_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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uint Opcode = 0xDAC01000; // CLZ X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("CLZ <Wd>, <Wn>")]
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public void Clz_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
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{
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uint Opcode = 0x5AC01000; // CLZ W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("RBIT <Xd>, <Xn>")]
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public void Rbit_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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uint Opcode = 0xDAC00000; // RBIT X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("RBIT <Wd>, <Wn>")]
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public void Rbit_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
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{
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uint Opcode = 0x5AC00000; // RBIT W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("REV16 <Xd>, <Xn>")]
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public void Rev16_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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uint Opcode = 0xDAC00400; // REV16 X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("REV16 <Wd>, <Wn>")]
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public void Rev16_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
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{
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uint Opcode = 0x5AC00400; // REV16 W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("REV32 <Xd>, <Xn>")]
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public void Rev32_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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uint Opcode = 0xDAC00800; // REV32 X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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[Test, Description("REV <Wd>, <Wn>")]
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public void Rev32_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
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{
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uint Opcode = 0x5AC00800; // REV W0, W0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Wn));
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Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
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uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
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Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
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}
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else
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{
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Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
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}
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}
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[Test, Description("REV64 <Xd>, <Xn>")]
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public void Rev64_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
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{
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uint Opcode = 0xDAC00C00; // REV64 X0, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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if (Rd != 31)
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{
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Bits Op = new Bits(Opcode);
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AArch64.X((int)Rn, new Bits(Xn));
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Base.Rev64(Op[9, 5], Op[4, 0]);
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ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
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Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
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}
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else
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{
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Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
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}
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}
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#endif
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}
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}
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