mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-17 13:18:51 +02:00
b956bbc32c
* Update AOpCodeTable.cs * Update AInstEmitSystem.cs * Update AInstEmitSimdHash.cs * Update ASoftFallback.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
140 lines
3.9 KiB
C#
140 lines
3.9 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.Translation;
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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#region "Sha1"
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public static void Sha1c_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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EmitVectorExtractZx(Context, Op.Rn, 0, 2);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashChoose));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha1h_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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EmitVectorExtractZx(Context, Op.Rn, 0, 2);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.FixedRotate));
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EmitScalarSet(Context, Op.Rd, 2);
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}
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public static void Sha1m_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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EmitVectorExtractZx(Context, Op.Rn, 0, 2);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashMajority));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha1p_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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EmitVectorExtractZx(Context, Op.Rn, 0, 2);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashParity));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha1su0_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Sha1SchedulePart1));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha1su1_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Sha1SchedulePart2));
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Context.EmitStvec(Op.Rd);
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}
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#endregion
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#region "Sha256"
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public static void Sha256h_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashLower));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha256h2_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashUpper));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha256su0_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Sha256SchedulePart1));
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Context.EmitStvec(Op.Rd);
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}
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public static void Sha256su1_V(AILEmitterCtx Context)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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Context.EmitLdvec(Op.Rd);
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Context.EmitLdvec(Op.Rn);
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Context.EmitLdvec(Op.Rm);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Sha256SchedulePart2));
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Context.EmitStvec(Op.Rd);
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}
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#endregion
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}
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}
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