mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-09-11 10:18:52 +02:00
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table |
||
---|---|---|
.. | ||
Aarch32Mode.cs | ||
CpuThreadState.cs | ||
ExecutionMode.cs | ||
Fpcr.cs | ||
FpExc.cs | ||
Fpsr.cs | ||
FpType.cs | ||
PState.cs | ||
Register.cs | ||
RegisterAlias.cs | ||
RegisterSize.cs | ||
RegisterType.cs | ||
RoundMode.cs |