mirror of
https://github.com/Ryujinx/Ryujinx.git
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45ce540b9b
* ARMeilleure: Add `GFNI` detection This is intended for utilizing the `gf2p8affineqb` instruction * ARMeilleure: Add `gf2p8affineqb` Not using the VEX or EVEX-form of this instruction is intentional. There are `GFNI`-chips that do not support AVX(so no VEX encoding) such as Tremont(Lakefield) chips as well as Jasper Lake.13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299)13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254)* ARMeilleure: Add `gfni` acceleration of `Rbit_V` Passes all `Rbit_V*` unit tests on my `i9-11900k` * ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V` Also added a fast-path for when the shift amount is greater than the size of the element. * ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V` * ARMeilleure: Increment InternalVersion * ARMeilleure: Fix Intrinsic and Assembler Table alignment `gf2p8affineqb` is the longest instruction name I know of. It shouldn't get any wider than this. * ARMeilleure: Remove SSE2+SHA requirement for GFNI * ARMeilleure Add `X86GetGf2p8LogicalShiftLeft` Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction. * ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`
177 lines
3.4 KiB
C#
177 lines
3.4 KiB
C#
namespace ARMeilleure.IntermediateRepresentation
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{
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enum Intrinsic : ushort
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{
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X86Addpd,
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X86Addps,
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X86Addsd,
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X86Addss,
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X86Aesdec,
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X86Aesdeclast,
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X86Aesenc,
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X86Aesenclast,
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X86Aesimc,
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X86Andnpd,
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X86Andnps,
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X86Andpd,
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X86Andps,
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X86Blendvpd,
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X86Blendvps,
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X86Cmppd,
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X86Cmpps,
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X86Cmpsd,
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X86Cmpss,
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X86Comisdeq,
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X86Comisdge,
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X86Comisdlt,
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X86Comisseq,
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X86Comissge,
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X86Comisslt,
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X86Crc32,
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X86Crc32_16,
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X86Crc32_8,
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X86Cvtdq2pd,
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X86Cvtdq2ps,
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X86Cvtpd2dq,
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X86Cvtpd2ps,
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X86Cvtps2dq,
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X86Cvtps2pd,
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X86Cvtsd2si,
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X86Cvtsd2ss,
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X86Cvtsi2sd,
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X86Cvtsi2si,
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X86Cvtsi2ss,
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X86Cvtss2sd,
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X86Cvtss2si,
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X86Divpd,
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X86Divps,
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X86Divsd,
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X86Divss,
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X86Gf2p8affineqb,
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X86Haddpd,
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X86Haddps,
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X86Insertps,
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X86Maxpd,
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X86Maxps,
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X86Maxsd,
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X86Maxss,
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X86Minpd,
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X86Minps,
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X86Minsd,
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X86Minss,
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X86Movhlps,
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X86Movlhps,
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X86Movss,
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X86Mulpd,
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X86Mulps,
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X86Mulsd,
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X86Mulss,
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X86Mxcsrmb,
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X86Mxcsrub,
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X86Paddb,
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X86Paddd,
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X86Paddq,
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X86Paddw,
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X86Palignr,
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X86Pand,
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X86Pandn,
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X86Pavgb,
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X86Pavgw,
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X86Pblendvb,
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X86Pclmulqdq,
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X86Pcmpeqb,
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X86Pcmpeqd,
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X86Pcmpeqq,
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X86Pcmpeqw,
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X86Pcmpgtb,
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X86Pcmpgtd,
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X86Pcmpgtq,
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X86Pcmpgtw,
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X86Pmaxsb,
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X86Pmaxsd,
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X86Pmaxsw,
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X86Pmaxub,
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X86Pmaxud,
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X86Pmaxuw,
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X86Pminsb,
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X86Pminsd,
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X86Pminsw,
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X86Pminub,
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X86Pminud,
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X86Pminuw,
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X86Pmovsxbw,
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X86Pmovsxdq,
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X86Pmovsxwd,
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X86Pmovzxbw,
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X86Pmovzxdq,
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X86Pmovzxwd,
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X86Pmulld,
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X86Pmullw,
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X86Popcnt,
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X86Por,
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X86Pshufb,
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X86Pshufd,
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X86Pslld,
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X86Pslldq,
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X86Psllq,
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X86Psllw,
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X86Psrad,
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X86Psraw,
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X86Psrld,
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X86Psrlq,
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X86Psrldq,
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X86Psrlw,
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X86Psubb,
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X86Psubd,
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X86Psubq,
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X86Psubw,
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X86Punpckhbw,
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X86Punpckhdq,
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X86Punpckhqdq,
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X86Punpckhwd,
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X86Punpcklbw,
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X86Punpckldq,
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X86Punpcklqdq,
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X86Punpcklwd,
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X86Pxor,
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X86Rcpps,
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X86Rcpss,
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X86Roundpd,
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X86Roundps,
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X86Roundsd,
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X86Roundss,
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X86Rsqrtps,
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X86Rsqrtss,
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X86Sha256Msg1,
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X86Sha256Msg2,
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X86Sha256Rnds2,
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X86Shufpd,
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X86Shufps,
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X86Sqrtpd,
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X86Sqrtps,
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X86Sqrtsd,
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X86Sqrtss,
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X86Subpd,
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X86Subps,
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X86Subsd,
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X86Subss,
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X86Unpckhpd,
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X86Unpckhps,
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X86Unpcklpd,
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X86Unpcklps,
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X86Vcvtph2ps,
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X86Vcvtps2ph,
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X86Vfmadd231ps,
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X86Vfmadd231sd,
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X86Vfmadd231ss,
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X86Vfmsub231sd,
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X86Vfmsub231ss,
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X86Vfnmadd231ps,
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X86Vfnmadd231sd,
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X86Vfnmadd231ss,
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X86Vfnmsub231sd,
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X86Vfnmsub231ss,
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X86Xorpd,
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X86Xorps
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}
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} |