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https://github.com/Ryujinx/Ryujinx.git
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* add 'ADC 32bit and Overflow' test * Add WZR/WSP tests * fix ADC and ADDS * add ADCS test * add SBCS test * indent my code and delete comment * '/' <- i hate you x) * remove spacebar char * remove false tab * add frintx_S test * update frintx_S test * add ASRV test * fix new line * fix PR * fix indent
163 lines
7.2 KiB
C#
163 lines
7.2 KiB
C#
using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestAlu : CpuTest
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{
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[TestCase(0x9A020020u, 2u, 3u, true, 6u)]
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[TestCase(0x9A020020u, 2u, 3u, false, 5u)]
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[TestCase(0x1A020020u, 2u, 3u, true, 6u)]
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[TestCase(0x1A020020u, 2u, 3u, false, 5u)]
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[TestCase(0x1A020020u, 0xFFFFFFFFu, 0x2u, false, 0x1u)]
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public void Adc(uint Opcode, uint A, uint B, bool CarryState, uint Result)
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{
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// ADC (X0/W0), (X1/W1), (X2/W2)
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState);
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Assert.AreEqual(Result, ThreadState.X0);
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}
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[TestCase(0x3A020020u, 2u, 3u, false, false, false, false, 5u)]
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[TestCase(0x3A020020u, 2u, 3u, true, false, false, false, 6u)]
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[TestCase(0xBA020020u, 2u, 3u, false, false, false, false, 5u)]
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[TestCase(0xBA020020u, 2u, 3u, true, false, false, false, 6u)]
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[TestCase(0x3A020020u, 0xFFFFFFFEu, 0x1u, true, false, true, true, 0x0u)]
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[TestCase(0x3A020020u, 0xFFFFFFFFu, 0xFFFFFFFFu, true, true, false, true, 0xFFFFFFFFu)]
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public void Adcs(uint Opcode, uint A, uint B, bool CarryState, bool Negative, bool Zero, bool Carry, uint Result)
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{
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//ADCS (X0/W0), (X1, W1), (X2/W2)
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState);
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Assert.Multiple(() =>
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{
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(Result, ThreadState.X0);
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});
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}
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[Test]
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public void Add()
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{
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// ADD X0, X1, X2
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AThreadState ThreadState = SingleOpcode(0x8B020020, X1: 1, X2: 2);
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Assert.AreEqual(3, ThreadState.X0);
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}
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[TestCase(2u, false, false)]
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[TestCase(5u, false, false)]
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[TestCase(7u, false, false)]
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[TestCase(0xFFFFFFFFu, false, true )]
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[TestCase(0xFFFFFFFBu, true, true )]
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public void Adds(uint A, bool Zero, bool Carry)
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{
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//ADDS WZR, WSP, #5
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AThreadState ThreadState = SingleOpcode(0x310017FF, X31: A);
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Assert.Multiple(() =>
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{
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Assert.IsFalse(ThreadState.Negative);
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(A, ThreadState.X31);
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});
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}
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[TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)]
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[TestCase(0xFFFFFFFFu, 0x00000000u, 0x00000000ul, false, true)]
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[TestCase(0x12345678u, 0x7324A993u, 0x12240010ul, false, false)]
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public void Ands(uint A, uint B, ulong Result, bool Negative, bool Zero)
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{
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// ANDS W0, W1, W2
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uint Opcode = 0x6A020020;
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result, ThreadState.X0);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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});
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}
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[TestCase(0x0000FF44u, 0x00000004u, 0x00000FF4u)]
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[TestCase(0x00000000u, 0x00000004u, 0x00000000u)]
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[TestCase(0x0000FF44u, 0x00000008u, 0x000000FFu)]
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[TestCase(0xFFFFFFFFu, 0x00000004u, 0xFFFFFFFFu)]
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[TestCase(0xFFFFFFFFu, 0x00000008u, 0xFFFFFFFFu)]
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[TestCase(0xFFFFFFFFu, 0x00000020u, 0xFFFFFFFFu)]
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[TestCase(0x0FFFFFFFu, 0x0000001Cu, 0x00000000u)]
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[TestCase(0x80000000u, 0x0000001Fu, 0xFFFFFFFFu)]
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[TestCase(0xCAFE0000u, 0x00000020u, 0xCAFE0000u)]
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public void Asrv32(uint A, uint ShiftValue, uint Result)
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{
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// ASRV W0, W1, W2
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AThreadState ThreadState = SingleOpcode(0x1AC22820, X1: A, X2: ShiftValue);
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Assert.AreEqual(Result, ThreadState.X0);
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}
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[TestCase(0x000000000000FF44ul, 0x00000004u, 0x0000000000000FF4ul)]
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[TestCase(0x0000000000000000ul, 0x00000004u, 0x0000000000000000ul)]
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[TestCase(0x000000000000FF44ul, 0x00000008u, 0x00000000000000FFul)]
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[TestCase(0x00000000FFFFFFFFul, 0x00000004u, 0x000000000FFFFFFFul)]
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[TestCase(0x00000000FFFFFFFFul, 0x00000008u, 0x0000000000FFFFFFul)]
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[TestCase(0x00000000FFFFFFFFul, 0x00000020u, 0x0000000000000000ul)]
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[TestCase(0x000000000FFFFFFFul, 0x0000001Cu, 0x0000000000000000ul)]
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[TestCase(0x000CC4488FFFFFFFul, 0x0000001Cu, 0x0000000000CC4488ul)]
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[TestCase(0xFFFFFFFFFFFFFFFFul, 0x0000001Cu, 0xFFFFFFFFFFFFFFFFul)]
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[TestCase(0x8000000000000000ul, 0x0000003Fu, 0xFFFFFFFFFFFFFFFFul)]
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[TestCase(0xCAFE000000000000ul, 0x00000040u, 0xCAFE000000000000ul)]
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public void Asrv64(ulong A, uint ShiftValue, ulong Result)
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{
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// ASRV X0, X1, X2
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AThreadState ThreadState = SingleOpcode(0x9AC22820, X1: A, X2: ShiftValue);
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Assert.AreEqual(Result, ThreadState.X0);
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}
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[TestCase(0x01010101u, 0x3200C3E2u)]
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[TestCase(0x00F000F0u, 0x320C8FE2u)]
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[TestCase(0x00000001u, 0x320003E2u)]
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public void OrrBitmasks(uint Bitmask, uint Opcode)
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{
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// ORR W2, WZR, #Bitmask
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Assert.AreEqual(Bitmask, SingleOpcode(Opcode).X2);
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}
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[Test]
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public void RevX0X0()
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{
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// REV X0, X0
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AThreadState ThreadState = SingleOpcode(0xDAC00C00, X0: 0xAABBCCDDEEFF1100);
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Assert.AreEqual(0x0011FFEEDDCCBBAA, ThreadState.X0);
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}
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[Test]
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public void RevW1W1()
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{
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// REV W1, W1
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AThreadState ThreadState = SingleOpcode(0x5AC00821, X1: 0x12345678);
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Assert.AreEqual(0x78563412, ThreadState.X1);
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}
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[TestCase(0x7A020020u, 4u, 2u, false, false, false, true, 1u)]
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[TestCase(0x7A020020u, 4u, 2u, true, false, false, true, 2u)]
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[TestCase(0xFA020020u, 4u, 2u, false, false, false, true, 1u)]
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[TestCase(0xFA020020u, 4u, 2u, true, false, false, true, 2u)]
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[TestCase(0x7A020020u, 4u, 4u, false, true, false, false, 0xFFFFFFFFu)]
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[TestCase(0x7A020020u, 4u, 4u, true, false, true, true, 0x0u)]
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public void Sbcs(uint Opcode, uint A, uint B, bool CarryState, bool Negative, bool Zero, bool Carry, uint Result)
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{
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//SBCS (X0/W0), (X1, W1), (X2/W2)
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState);
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Assert.Multiple(() =>
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{
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Assert.IsFalse(ThreadState.Overflow);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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Assert.AreEqual(Carry, ThreadState.Carry);
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Assert.AreEqual(Result, ThreadState.X0);
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});
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}
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}
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}
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