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Aarch32Mode.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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ExecutionContext.cs
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IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special handling from kernel (#1458)
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2020-12-02 00:23:43 +01:00 |
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ExecutionMode.cs
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Added a simple PtcFormatter library for deserialization/serialization, which does not require reflection, in use at PtcJumpTable and PtcProfiler; improves maintainability and simplicity/readability of affected code.
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2021-02-14 03:04:12 +01:00 |
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FPCR.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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FPException.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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FPRoundingMode.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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FPSR.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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FPState.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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FPType.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstExceptionEventArgs.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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InstUndefinedEventArgs.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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NativeContext.cs
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Implement inline memory load/store exclusive and ordered (#1413)
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2020-07-30 11:29:28 -03:00 |
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PState.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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RegisterAlias.cs
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Add most of the A32 instruction set to ARMeilleure (#897)
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2020-02-24 08:20:40 +11:00 |
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RegisterConsts.cs
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Add most of the A32 instruction set to ARMeilleure (#897)
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2020-02-24 08:20:40 +11:00 |
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V128.cs
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CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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2021-01-04 23:45:54 +01:00 |
