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* Initial tessellation shader support * Nits * Re-arrange built-in table * This is not needed anymore * PR feedback
341 lines
12 KiB
C#
341 lines
12 KiB
C#
using Ryujinx.Graphics.Shader.CodeGen.Glsl;
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.StructuredIr;
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using Ryujinx.Graphics.Shader.Translation.Optimizations;
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using System;
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using System.Collections.Generic;
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using System.Numerics;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Translation
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{
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public static class Translator
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{
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private const int HeaderSize = 0x50;
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internal struct FunctionCode
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{
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public Operation[] Code { get; }
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public FunctionCode(Operation[] code)
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{
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Code = code;
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}
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}
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public static TranslatorContext CreateContext(
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ulong address,
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IGpuAccessor gpuAccessor,
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TranslationOptions options,
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TranslationCounts counts = null)
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{
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counts ??= new TranslationCounts();
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Block[][] cfg = DecodeShader(address, gpuAccessor, options, counts, out ShaderConfig config);
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return new TranslatorContext(address, cfg, config);
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}
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internal static ShaderProgram Translate(FunctionCode[] functions, ShaderConfig config, out ShaderProgramInfo shaderProgramInfo)
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{
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var cfgs = new ControlFlowGraph[functions.Length];
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var frus = new RegisterUsage.FunctionRegisterUsage[functions.Length];
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for (int i = 0; i < functions.Length; i++)
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{
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cfgs[i] = ControlFlowGraph.Create(functions[i].Code);
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if (i != 0)
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{
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frus[i] = RegisterUsage.RunPass(cfgs[i]);
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}
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}
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Function[] funcs = new Function[functions.Length];
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for (int i = 0; i < functions.Length; i++)
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{
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var cfg = cfgs[i];
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int inArgumentsCount = 0;
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int outArgumentsCount = 0;
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if (i != 0)
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{
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var fru = frus[i];
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inArgumentsCount = fru.InArguments.Length;
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outArgumentsCount = fru.OutArguments.Length;
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}
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if (cfg.Blocks.Length != 0)
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{
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RegisterUsage.FixupCalls(cfg.Blocks, frus);
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Dominance.FindDominators(cfg);
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Dominance.FindDominanceFrontiers(cfg.Blocks);
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Ssa.Rename(cfg.Blocks);
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Optimizer.RunPass(cfg.Blocks, config);
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Rewriter.RunPass(cfg.Blocks, config);
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}
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funcs[i] = new Function(cfg.Blocks, $"fun{i}", false, inArgumentsCount, outArgumentsCount);
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}
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StructuredProgramInfo sInfo = StructuredProgram.MakeStructuredProgram(funcs, config);
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ShaderProgram program;
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switch (config.Options.TargetLanguage)
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{
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case TargetLanguage.Glsl:
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program = new ShaderProgram(config.Stage, GlslGenerator.Generate(sInfo, config));
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break;
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default:
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throw new NotImplementedException(config.Options.TargetLanguage.ToString());
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}
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shaderProgramInfo = new ShaderProgramInfo(
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config.GetConstantBufferDescriptors(),
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config.GetStorageBufferDescriptors(),
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config.GetTextureDescriptors(),
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config.GetImageDescriptors(),
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config.UsedFeatures.HasFlag(FeatureFlags.InstanceId),
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config.UsedFeatures.HasFlag(FeatureFlags.RtLayer),
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config.ClipDistancesWritten);
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return program;
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}
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private static Block[][] DecodeShader(
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ulong address,
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IGpuAccessor gpuAccessor,
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TranslationOptions options,
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TranslationCounts counts,
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out ShaderConfig config)
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{
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Block[][] cfg;
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ulong maxEndAddress = 0;
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if ((options.Flags & TranslationFlags.Compute) != 0)
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{
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config = new ShaderConfig(gpuAccessor, options, counts);
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cfg = Decoder.Decode(config, address);
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}
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else
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{
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config = new ShaderConfig(new ShaderHeader(gpuAccessor, address), gpuAccessor, options, counts);
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cfg = Decoder.Decode(config, address + HeaderSize);
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}
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for (int funcIndex = 0; funcIndex < cfg.Length; funcIndex++)
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{
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for (int blkIndex = 0; blkIndex < cfg[funcIndex].Length; blkIndex++)
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{
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Block block = cfg[funcIndex][blkIndex];
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if (maxEndAddress < block.EndAddress)
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{
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maxEndAddress = block.EndAddress;
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}
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if (!config.UsedFeatures.HasFlag(FeatureFlags.Bindless))
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{
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for (int index = 0; index < block.OpCodes.Count; index++)
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{
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InstOp op = block.OpCodes[index];
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if (op.Props.HasFlag(InstProps.Tex))
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{
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int tidB = (int)((op.RawOpCode >> 36) & 0x1fff);
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config.TextureHandlesForCache.Add(tidB);
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}
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}
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}
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}
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}
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config.SizeAdd((int)maxEndAddress + (options.Flags.HasFlag(TranslationFlags.Compute) ? 0 : HeaderSize));
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return cfg;
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}
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internal static FunctionCode[] EmitShader(Block[][] cfg, ShaderConfig config, bool initializeOutputs, out int initializationOperations)
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{
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initializationOperations = 0;
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Dictionary<ulong, int> funcIds = new Dictionary<ulong, int>();
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for (int funcIndex = 0; funcIndex < cfg.Length; funcIndex++)
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{
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funcIds.Add(cfg[funcIndex][0].Address, funcIndex);
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}
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List<FunctionCode> funcs = new List<FunctionCode>();
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for (int funcIndex = 0; funcIndex < cfg.Length; funcIndex++)
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{
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EmitterContext context = new EmitterContext(config, funcIndex != 0, funcIds);
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if (initializeOutputs && funcIndex == 0)
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{
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EmitOutputsInitialization(context, config);
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initializationOperations = context.OperationsCount;
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}
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for (int blkIndex = 0; blkIndex < cfg[funcIndex].Length; blkIndex++)
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{
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Block block = cfg[funcIndex][blkIndex];
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context.CurrBlock = block;
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context.MarkLabel(context.GetLabel(block.Address));
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EmitOps(context, block);
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}
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funcs.Add(new FunctionCode(context.GetOperations()));
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}
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return funcs.ToArray();
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}
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private static void EmitOutputsInitialization(EmitterContext context, ShaderConfig config)
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{
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// Compute has no output attributes, and fragment is the last stage, so we
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// don't need to initialize outputs on those stages.
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if (config.Stage == ShaderStage.Compute || config.Stage == ShaderStage.Fragment)
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{
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return;
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}
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if (config.Stage == ShaderStage.Vertex)
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{
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InitializeOutput(context, AttributeConsts.PositionX, perPatch: false);
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}
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int usedAttributes = context.Config.UsedOutputAttributes;
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while (usedAttributes != 0)
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{
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int index = BitOperations.TrailingZeroCount(usedAttributes);
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InitializeOutput(context, AttributeConsts.UserAttributeBase + index * 16, perPatch: false);
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usedAttributes &= ~(1 << index);
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}
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int usedAttributesPerPatch = context.Config.UsedOutputAttributesPerPatch;
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while (usedAttributesPerPatch != 0)
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{
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int index = BitOperations.TrailingZeroCount(usedAttributesPerPatch);
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InitializeOutput(context, AttributeConsts.UserAttributeBase + index * 16, perPatch: true);
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usedAttributesPerPatch &= ~(1 << index);
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}
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}
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private static void InitializeOutput(EmitterContext context, int baseAttr, bool perPatch)
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{
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for (int c = 0; c < 4; c++)
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{
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int attrOffset = baseAttr + c * 4;
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context.Copy(perPatch ? AttributePerPatch(attrOffset) : Attribute(attrOffset), ConstF(c == 3 ? 1f : 0f));
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}
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}
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private static void EmitOps(EmitterContext context, Block block)
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{
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for (int opIndex = 0; opIndex < block.OpCodes.Count; opIndex++)
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{
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InstOp op = block.OpCodes[opIndex];
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if (context.Config.Options.Flags.HasFlag(TranslationFlags.DebugMode))
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{
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string instName;
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if (op.Emitter != null)
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{
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instName = op.Name.ToString();
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}
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else
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{
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instName = "???";
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context.Config.GpuAccessor.Log($"Invalid instruction at 0x{op.Address:X6} (0x{op.RawOpCode:X16}).");
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}
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string dbgComment = $"0x{op.Address:X6}: 0x{op.RawOpCode:X16} {instName}";
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context.Add(new CommentNode(dbgComment));
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}
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InstConditional opConditional = new InstConditional(op.RawOpCode);
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bool noPred = op.Props.HasFlag(InstProps.NoPred);
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if (!noPred && opConditional.Pred == RegisterConsts.PredicateTrueIndex && opConditional.PredInv)
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{
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continue;
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}
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Operand predSkipLbl = null;
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if (op.Name == InstName.Sync || op.Name == InstName.Brk)
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{
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// If the instruction is a SYNC or BRK instruction with only one
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// possible target address, then the instruction is basically
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// just a simple branch, we can generate code similar to branch
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// instructions, with the condition check on the branch itself.
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noPred = block.SyncTargets.Count <= 1;
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}
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else if (op.Name == InstName.Bra)
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{
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noPred = true;
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}
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if (!(opConditional.Pred == RegisterConsts.PredicateTrueIndex || noPred))
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{
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Operand label;
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if (opIndex == block.OpCodes.Count - 1 && block.HasNext())
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{
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label = context.GetLabel(block.Successors[0].Address);
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}
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else
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{
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label = Label();
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predSkipLbl = label;
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}
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Operand pred = Register(opConditional.Pred, RegisterType.Predicate);
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if (opConditional.PredInv)
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{
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context.BranchIfTrue(label, pred);
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}
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else
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{
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context.BranchIfFalse(label, pred);
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}
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}
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context.CurrOp = op;
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op.Emitter?.Invoke(context);
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if (predSkipLbl != null)
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{
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context.MarkLabel(predSkipLbl);
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}
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}
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}
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}
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} |