mirror of
https://github.com/Ryujinx/Ryujinx.git
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5e724cf24e
* Delete DelegateTypes.cs * Delete DelegateCache.cs * Add files via upload * Update Horizon.cs * Update Program.cs * Update MainWindow.cs * Update Aot.cs * Update RelocEntry.cs * Update Translator.cs * Update MemoryManager.cs * Update InstEmitMemoryHelper.cs * Update Delegates.cs * Nit. * Nit. * Nit. * 10 fewer MSIL bytes for us * Add comment. Nits. * Update Translator.cs * Update Aot.cs * Nits. * Opt.. * Opt.. * Opt.. * Opt.. * Allow to change compression level. * Update MemoryManager.cs * Update Translator.cs * Manage corner cases during the save phase. Nits. * Update Aot.cs * Translator response tweak for Aot disabled. Nit. * Nit. * Nits. * Create DelegateHelpers.cs * Update Delegates.cs * Nit. * Nit. * Nits. * Fix due to #784. * Fixes due to #757 & #841. * Fix due to #846. * Fix due to #847. * Use MethodInfo for managed method calls. Use IR methods instead of managed methods about Max/Min (S/U). Follow-ups & Nits. * Add missing exception messages. Reintroduce slow path for Fmov_Vi. Implement slow path for Fmov_Si. * Switch to the new folder structure. Nits. * Impl. index-based relocation information. Impl. cache file version field. * Nit. * Address gdkchan comments. Mainly: - fixed cache file corruption issue on exit; - exposed a way to disable AOT on the GUI. * Address AcK77 comment. * Address Thealexbarney, jduncanator & emmauss comments. Header magic, CpuId (FI) & Aot -> Ptc. * Adaptation to the new application reloading system. Improvements to the call system of managed methods. Follow-ups. Nits. * Get the same boot times as on master when PTC is disabled. * Profiled Aot. * A32 support (#897). * #975 support (1 of 2). * #975 support (2 of 2). * Rebase fix & nits. * Some fixes and nits (still one bug left). * One fix & nits. * Tests fix (by gdk) & nits. * Support translations not only in high quality and rejit. Nits. * Added possibility to skip translations and continue execution, using `ESC` key. * Update SettingsWindow.cs * Update GLRenderer.cs * Update Ptc.cs * Disabled Profiled PTC by default as requested in the past by gdk. * Fix rejit bug. Increased number of parallel translations. Add stack unwinding stuffs support (1 of 2). Nits. * Add stack unwinding stuffs support (2 of 2). Tuned number of parallel translations. * Restored the ability to assemble jumps with 8-bit offset when Profiled PTC is disabled or during profiling. Modifications due to rebase. Nits. * Limited profiling of the functions to be translated to the addresses belonging to the range of static objects only. * Nits. * Nits. * Update Delegates.cs * Nit. * Update InstEmitSimdArithmetic.cs * Address riperiperi comments. * Fixed the issue of unjustifiably longer boot times at the second boot than at the first boot, measured at the same time or reference point and with the same number of translated functions. * Implemented a simple redundant load/save mechanism. Halved the value of Decoder.MaxInstsPerFunction more appropriate for the current performance of the Translator. Replaced by Logger.PrintError to Logger.PrintDebug in TexturePool.cs about the supposed invalid texture format to avoid the spawn of the log. Nits. * Nit. Improved Logger.PrintError in TexturePool.cs to avoid log spawn. Added missing code for FZ handling (in output) for fp max/min instructions (slow paths). * Add configuration migration for PTC Co-authored-by: Thog <me@thog.eu>
851 lines
28 KiB
C#
851 lines
28 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using System.Collections.Generic;
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using System.Reflection;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitSimdHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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#region "Masks"
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private static readonly long[] _masksE0_Uzp = new long[]
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{
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13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0,
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11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0
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};
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private static readonly long[] _masksE1_Uzp = new long[]
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{
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15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0,
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15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0
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};
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#endregion
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public static void Dup_Gp(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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if (Optimizations.UseSse2)
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{
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switch (op.Size)
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{
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case 0: n = context.ZeroExtend8 (n.Type, n); n = context.Multiply(n, Const(n.Type, 0x01010101)); break;
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case 1: n = context.ZeroExtend16(n.Type, n); n = context.Multiply(n, Const(n.Type, 0x00010001)); break;
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case 2: n = context.ZeroExtend32(n.Type, n); break;
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}
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Operand res = context.VectorInsert(context.VectorZero(), n, 0);
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if (op.Size < 3)
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{
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0xf0));
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}
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else
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{
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0));
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}
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}
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else
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{
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res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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res = EmitVectorInsert(context, res, n, index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Dup_S(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand ne = EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
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context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), ne, 0, op.Size));
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}
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public static void Dup_V(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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Operand res = GetVec(op.Rn);
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if (op.Size == 0)
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{
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if (op.DstIndex != 0)
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{
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res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(op.DstIndex));
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}
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res = context.AddIntrinsic(Intrinsic.X86Punpcklbw, res, res);
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res = context.AddIntrinsic(Intrinsic.X86Punpcklwd, res, res);
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0));
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}
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else if (op.Size == 1)
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{
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if (op.DstIndex != 0)
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{
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res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(op.DstIndex * 2));
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}
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res = context.AddIntrinsic(Intrinsic.X86Punpcklwd, res, res);
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(0));
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}
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else if (op.Size == 2)
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{
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int mask = op.DstIndex * 0b01010101;
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res = context.AddIntrinsic(Intrinsic.X86Shufps, res, res, Const(mask));
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}
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else if (op.DstIndex == 0 && op.RegisterSize != RegisterSize.Simd64)
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{
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res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, res);
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}
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else if (op.DstIndex == 1)
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{
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res = context.AddIntrinsic(Intrinsic.X86Movhlps, res, res);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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res = context.VectorZeroUpper64(res);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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Operand ne = EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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res = EmitVectorInsert(context, res, ne, index, op.Size);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Ext_V(ArmEmitterContext context)
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{
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OpCodeSimdExt op = (OpCodeSimdExt)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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Operand nShifted = GetVec(op.Rn);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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nShifted = context.VectorZeroUpper64(nShifted);
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}
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nShifted = context.AddIntrinsic(Intrinsic.X86Psrldq, nShifted, Const(op.Imm4));
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Operand mShifted = GetVec(op.Rm);
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mShifted = context.AddIntrinsic(Intrinsic.X86Pslldq, mShifted, Const(op.GetBytesCount() - op.Imm4));
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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mShifted = context.VectorZeroUpper64(mShifted);
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}
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Operand res = context.AddIntrinsic(Intrinsic.X86Por, nShifted, mShifted);
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context.Copy(GetVec(op.Rd), res);
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}
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else
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{
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Operand res = context.VectorZero();
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int bytes = op.GetBytesCount();
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int position = op.Imm4 & (bytes - 1);
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for (int index = 0; index < bytes; index++)
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{
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int reg = op.Imm4 + index < bytes ? op.Rn : op.Rm;
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Operand e = EmitVectorExtractZx(context, reg, position, 0);
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position = (position + 1) & (bytes - 1);
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res = EmitVectorInsert(context, res, e, index, 0);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Fcsel_S(ArmEmitterContext context)
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{
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OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp;
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Operand lblTrue = Label();
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Operand lblEnd = Label();
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Operand isTrue = InstEmitFlowHelper.GetCondTrue(context, op.Cond);
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context.BranchIfTrue(lblTrue, isTrue);
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OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
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Operand me = context.VectorExtract(type, GetVec(op.Rm), 0);
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), me, 0));
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context.Branch(lblEnd);
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context.MarkLabel(lblTrue);
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Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), ne, 0));
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context.MarkLabel(lblEnd);
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}
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public static void Fmov_Ftoi(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand ne = EmitVectorExtractZx(context, op.Rn, 0, op.Size + 2);
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SetIntOrZR(context, op.Rd, ne);
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}
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public static void Fmov_Ftoi1(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand ne = EmitVectorExtractZx(context, op.Rn, 1, 3);
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SetIntOrZR(context, op.Rd, ne);
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}
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public static void Fmov_Itof(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand n = GetIntOrZR(context, op.Rn);
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context.Copy(GetVec(op.Rd), EmitVectorInsert(context, context.VectorZero(), n, 0, op.Size + 2));
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}
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public static void Fmov_Itof1(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetIntOrZR(context, op.Rn);
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context.Copy(d, EmitVectorInsert(context, d, n, 1, 3));
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}
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public static void Fmov_S(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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OperandType type = op.Size == 0 ? OperandType.FP32 : OperandType.FP64;
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Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), ne, 0));
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}
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public static void Fmov_Si(ArmEmitterContext context)
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{
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OpCodeSimdFmov op = (OpCodeSimdFmov)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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if (op.Size == 0)
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{
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context.Copy(GetVec(op.Rd), X86GetScalar(context, (int)op.Immediate));
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}
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else
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{
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context.Copy(GetVec(op.Rd), X86GetScalar(context, op.Immediate));
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}
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}
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else
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{
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Operand e = Const(op.Immediate);
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Operand res = context.VectorZero();
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res = EmitVectorInsert(context, res, e, 0, op.Size + 2);
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Fmov_Vi(ArmEmitterContext context)
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{
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OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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if (op.RegisterSize == RegisterSize.Simd128)
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{
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context.Copy(GetVec(op.Rd), X86GetAllElements(context, op.Immediate));
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}
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else
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{
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context.Copy(GetVec(op.Rd), X86GetScalar(context, op.Immediate));
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}
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}
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else
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{
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Operand e = Const(op.Immediate);
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Operand res = context.VectorZero();
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 2 : 1;
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for (int index = 0; index < elems; index++)
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{
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res = EmitVectorInsert(context, res, e, index, 3);
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}
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context.Copy(GetVec(op.Rd), res);
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}
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}
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public static void Ins_Gp(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand n = GetIntOrZR(context, op.Rn);
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context.Copy(d, EmitVectorInsert(context, d, n, op.DstIndex, op.Size));
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}
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public static void Ins_V(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand d = GetVec(op.Rd);
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Operand ne = EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size);
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context.Copy(d, EmitVectorInsert(context, d, ne, op.DstIndex, op.Size));
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}
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public static void Movi_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitSse2VectorMoviMvniOp(context, not: false);
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}
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else
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{
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EmitVectorImmUnaryOp(context, (op1) => op1);
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}
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}
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public static void Mvni_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse2)
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{
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EmitSse2VectorMoviMvniOp(context, not: true);
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}
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else
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{
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EmitVectorImmUnaryOp(context, (op1) => context.BitwiseNot(op1));
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}
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}
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public static void Smov_S(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand ne = EmitVectorExtractSx(context, op.Rn, op.DstIndex, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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ne = context.ZeroExtend32(OperandType.I64, ne);
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}
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SetIntOrZR(context, op.Rd, ne);
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}
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public static void Tbl_V(ArmEmitterContext context)
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{
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EmitTableVectorLookup(context, isTbl: true);
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}
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public static void Tbx_V(ArmEmitterContext context)
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{
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EmitTableVectorLookup(context, isTbl: false);
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}
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public static void Trn1_V(ArmEmitterContext context)
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{
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EmitVectorTranspose(context, part: 0);
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}
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public static void Trn2_V(ArmEmitterContext context)
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{
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EmitVectorTranspose(context, part: 1);
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}
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public static void Umov_S(ArmEmitterContext context)
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{
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OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp;
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Operand ne = EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size);
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SetIntOrZR(context, op.Rd, ne);
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}
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public static void Uzp1_V(ArmEmitterContext context)
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{
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EmitVectorUnzip(context, part: 0);
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}
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public static void Uzp2_V(ArmEmitterContext context)
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{
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EmitVectorUnzip(context, part: 1);
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}
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public static void Xtn_V(ArmEmitterContext context)
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{
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OpCodeSimd op = (OpCodeSimd)context.CurrOp;
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if (Optimizations.UseSsse3)
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{
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Operand d = GetVec(op.Rd);
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Operand res = context.VectorZeroUpper64(d);
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Operand mask = X86GetAllElements(context, EvenMasks[op.Size]);
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Operand res2 = context.AddIntrinsic(Intrinsic.X86Pshufb, GetVec(op.Rn), mask);
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Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128
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? Intrinsic.X86Movlhps
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: Intrinsic.X86Movhlps;
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res = context.AddIntrinsic(movInst, res, res2);
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context.Copy(d, res);
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}
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else
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{
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int elems = 8 >> op.Size;
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int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0;
|
|
|
|
Operand d = GetVec(op.Rd);
|
|
|
|
Operand res = part == 0 ? context.VectorZero() : context.Copy(d);
|
|
|
|
for (int index = 0; index < elems; index++)
|
|
{
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size + 1);
|
|
|
|
res = EmitVectorInsert(context, res, ne, part + index, op.Size);
|
|
}
|
|
|
|
context.Copy(d, res);
|
|
}
|
|
}
|
|
|
|
public static void Zip1_V(ArmEmitterContext context)
|
|
{
|
|
EmitVectorZip(context, part: 0);
|
|
}
|
|
|
|
public static void Zip2_V(ArmEmitterContext context)
|
|
{
|
|
EmitVectorZip(context, part: 1);
|
|
}
|
|
|
|
private static void EmitSse2VectorMoviMvniOp(ArmEmitterContext context, bool not)
|
|
{
|
|
OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp;
|
|
|
|
long imm = op.Immediate;
|
|
|
|
switch (op.Size)
|
|
{
|
|
case 0: imm *= 0x01010101; break;
|
|
case 1: imm *= 0x00010001; break;
|
|
}
|
|
|
|
if (not)
|
|
{
|
|
imm = ~imm;
|
|
}
|
|
|
|
Operand mask;
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
mask = X86GetAllElements(context, (int)imm);
|
|
}
|
|
else
|
|
{
|
|
mask = X86GetAllElements(context, imm);
|
|
}
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
mask = context.VectorZeroUpper64(mask);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), mask);
|
|
}
|
|
|
|
private static void EmitTableVectorLookup(ArmEmitterContext context, bool isTbl)
|
|
{
|
|
OpCodeSimdTbl op = (OpCodeSimdTbl)context.CurrOp;
|
|
|
|
if (Optimizations.UseSsse3)
|
|
{
|
|
Operand d = GetVec(op.Rd);
|
|
Operand m = GetVec(op.Rm);
|
|
|
|
Operand res;
|
|
|
|
Operand mask = X86GetAllElements(context, 0x0F0F0F0F0F0F0F0FL);
|
|
|
|
// Fast path for single register table.
|
|
{
|
|
Operand n = GetVec(op.Rn);
|
|
|
|
Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, mask);
|
|
mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m);
|
|
|
|
res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mMask);
|
|
}
|
|
|
|
for (int index = 1; index < op.Size; index++)
|
|
{
|
|
Operand ni = GetVec((op.Rn + index) & 0x1F);
|
|
|
|
Operand idxMask = X86GetAllElements(context, 0x1010101010101010L * index);
|
|
|
|
Operand mSubMask = context.AddIntrinsic(Intrinsic.X86Psubb, m, idxMask);
|
|
|
|
Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, mSubMask, mask);
|
|
mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask);
|
|
|
|
Operand res2 = context.AddIntrinsic(Intrinsic.X86Pshufb, ni, mMask);
|
|
|
|
res = context.AddIntrinsic(Intrinsic.X86Por, res, res2);
|
|
}
|
|
|
|
if (!isTbl)
|
|
{
|
|
Operand idxMask = X86GetAllElements(context, (0x1010101010101010L * op.Size) - 0x0101010101010101L);
|
|
Operand zeroMask = context.VectorZero();
|
|
|
|
Operand mPosMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, idxMask);
|
|
Operand mNegMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, zeroMask, m);
|
|
|
|
Operand mMask = context.AddIntrinsic(Intrinsic.X86Por, mPosMask, mNegMask);
|
|
|
|
Operand dMask = context.AddIntrinsic(Intrinsic.X86Pand, d, mMask);
|
|
|
|
res = context.AddIntrinsic(Intrinsic.X86Por, res, dMask);
|
|
}
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
res = context.VectorZeroUpper64(res);
|
|
}
|
|
|
|
context.Copy(d, res);
|
|
}
|
|
else
|
|
{
|
|
Operand d = GetVec(op.Rd);
|
|
|
|
List<Operand> args = new List<Operand>();
|
|
|
|
if (!isTbl)
|
|
{
|
|
args.Add(d);
|
|
}
|
|
|
|
args.Add(GetVec(op.Rm));
|
|
|
|
args.Add(Const(op.RegisterSize == RegisterSize.Simd64 ? 8 : 16));
|
|
|
|
for (int index = 0; index < op.Size; index++)
|
|
{
|
|
args.Add(GetVec((op.Rn + index) & 0x1F));
|
|
}
|
|
|
|
MethodInfo info = null;
|
|
|
|
if (isTbl)
|
|
{
|
|
switch (op.Size)
|
|
{
|
|
case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)); break;
|
|
case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)); break;
|
|
case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3)); break;
|
|
case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4)); break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (op.Size)
|
|
{
|
|
case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1)); break;
|
|
case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)); break;
|
|
case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)); break;
|
|
case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)); break;
|
|
}
|
|
}
|
|
|
|
context.Copy(d, context.Call(info, args.ToArray()));
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorTranspose(ArmEmitterContext context, int part)
|
|
{
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
|
|
|
if (Optimizations.UseSsse3)
|
|
{
|
|
Operand mask = null;
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
long maskE0 = EvenMasks[op.Size];
|
|
long maskE1 = OddMasks [op.Size];
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
}
|
|
|
|
Operand n = GetVec(op.Rn);
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
n = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
|
|
}
|
|
|
|
Operand m = GetVec(op.Rm);
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
m = context.AddIntrinsic(Intrinsic.X86Pshufb, m, mask);
|
|
}
|
|
|
|
Intrinsic punpckInst = part == 0
|
|
? X86PunpcklInstruction[op.Size]
|
|
: X86PunpckhInstruction[op.Size];
|
|
|
|
Operand res = context.AddIntrinsic(punpckInst, n, m);
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd64)
|
|
{
|
|
res = context.VectorZeroUpper64(res);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else
|
|
{
|
|
Operand res = context.VectorZero();
|
|
|
|
int pairs = op.GetPairsCount() >> op.Size;
|
|
|
|
for (int index = 0; index < pairs; index++)
|
|
{
|
|
int pairIndex = index << 1;
|
|
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, pairIndex + part, op.Size);
|
|
Operand me = EmitVectorExtractZx(context, op.Rm, pairIndex + part, op.Size);
|
|
|
|
res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
|
|
res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorUnzip(ArmEmitterContext context, int part)
|
|
{
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
|
|
|
if (Optimizations.UseSsse3)
|
|
{
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
|
{
|
|
Operand mask = null;
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
long maskE0 = EvenMasks[op.Size];
|
|
long maskE1 = OddMasks [op.Size];
|
|
|
|
mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
}
|
|
|
|
Operand n = GetVec(op.Rn);
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
n = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
|
|
}
|
|
|
|
Operand m = GetVec(op.Rm);
|
|
|
|
if (op.Size < 3)
|
|
{
|
|
m = context.AddIntrinsic(Intrinsic.X86Pshufb, m, mask);
|
|
}
|
|
|
|
Intrinsic punpckInst = part == 0
|
|
? Intrinsic.X86Punpcklqdq
|
|
: Intrinsic.X86Punpckhqdq;
|
|
|
|
Operand res = context.AddIntrinsic(punpckInst, n, m);
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else
|
|
{
|
|
Operand n = GetVec(op.Rn);
|
|
Operand m = GetVec(op.Rm);
|
|
|
|
Intrinsic punpcklInst = X86PunpcklInstruction[op.Size];
|
|
|
|
Operand res = context.AddIntrinsic(punpcklInst, n, m);
|
|
|
|
if (op.Size < 2)
|
|
{
|
|
long maskE0 = _masksE0_Uzp[op.Size];
|
|
long maskE1 = _masksE1_Uzp[op.Size];
|
|
|
|
Operand mask = X86GetScalar(context, maskE0);
|
|
|
|
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
|
|
|
|
res = context.AddIntrinsic(Intrinsic.X86Pshufb, res, mask);
|
|
}
|
|
|
|
Intrinsic punpckInst = part == 0
|
|
? Intrinsic.X86Punpcklqdq
|
|
: Intrinsic.X86Punpckhqdq;
|
|
|
|
res = context.AddIntrinsic(punpckInst, res, context.VectorZero());
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Operand res = context.VectorZero();
|
|
|
|
int pairs = op.GetPairsCount() >> op.Size;
|
|
|
|
for (int index = 0; index < pairs; index++)
|
|
{
|
|
int idx = index << 1;
|
|
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, idx + part, op.Size);
|
|
Operand me = EmitVectorExtractZx(context, op.Rm, idx + part, op.Size);
|
|
|
|
res = EmitVectorInsert(context, res, ne, index, op.Size);
|
|
res = EmitVectorInsert(context, res, me, pairs + index, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
|
|
private static void EmitVectorZip(ArmEmitterContext context, int part)
|
|
{
|
|
OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
|
|
|
|
if (Optimizations.UseSse2)
|
|
{
|
|
Operand n = GetVec(op.Rn);
|
|
Operand m = GetVec(op.Rm);
|
|
|
|
if (op.RegisterSize == RegisterSize.Simd128)
|
|
{
|
|
Intrinsic punpckInst = part == 0
|
|
? X86PunpcklInstruction[op.Size]
|
|
: X86PunpckhInstruction[op.Size];
|
|
|
|
Operand res = context.AddIntrinsic(punpckInst, n, m);
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
else
|
|
{
|
|
Operand res = context.AddIntrinsic(X86PunpcklInstruction[op.Size], n, m);
|
|
|
|
Intrinsic punpckInst = part == 0
|
|
? Intrinsic.X86Punpcklqdq
|
|
: Intrinsic.X86Punpckhqdq;
|
|
|
|
res = context.AddIntrinsic(punpckInst, res, context.VectorZero());
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
Operand res = context.VectorZero();
|
|
|
|
int pairs = op.GetPairsCount() >> op.Size;
|
|
|
|
int baseIndex = part != 0 ? pairs : 0;
|
|
|
|
for (int index = 0; index < pairs; index++)
|
|
{
|
|
int pairIndex = index << 1;
|
|
|
|
Operand ne = EmitVectorExtractZx(context, op.Rn, baseIndex + index, op.Size);
|
|
Operand me = EmitVectorExtractZx(context, op.Rm, baseIndex + index, op.Size);
|
|
|
|
res = EmitVectorInsert(context, res, ne, pairIndex, op.Size);
|
|
res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size);
|
|
}
|
|
|
|
context.Copy(GetVec(op.Rd), res);
|
|
}
|
|
}
|
|
}
|
|
}
|