Ryujinx/ARMeilleure/IntermediateRepresentation
merry f5235fff29
ARMeilleure: Hardware accelerate SHA256 (#3585)
* ARMeilleure/HardwareCapabilities: Add Sha

* ARMeilleure/Intrinsic: Add X86Sha256Rnds2

* ARmeilleure: Hardware accelerate SHA256H/SHA256H2

* ARMeilleure/Intrinsic: Add X86Sha256Msg1, X86Sha256Msg2

* ARMeilleure/Intrinsic: Add X86Palignr

* ARMeilleure: Hardware accelerate SHA256SU0, SHA256SU1

* PTC: Bump InternalVersion
2022-08-25 10:12:13 +00:00
..
BasicBlock.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
BasicBlockFrequency.cs
Comparison.cs
IIntrusiveListNode.cs
Instruction.cs
Intrinsic.cs ARMeilleure: Hardware accelerate SHA256 (#3585) 2022-08-25 10:12:13 +00:00
IntrusiveList.cs
MemoryOperand.cs
Multiplier.cs
Operand.cs Extend uses count from ushort to uint on Operand Data structure (#3374) 2022-06-05 14:15:27 -03:00
OperandKind.cs
OperandType.cs
Operation.cs
PhiOperation.cs
Register.cs
RegisterType.cs