Ryujinx/ARMeilleure/Translation/ControlFlowGraph.cs
gdkchan a731ab3a2a Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 21:56:22 +03:00

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4.6 KiB
C#

using ARMeilleure.IntermediateRepresentation;
using System;
using System.Collections.Generic;
using System.Diagnostics;
namespace ARMeilleure.Translation
{
class ControlFlowGraph
{
public BasicBlock Entry { get; }
public LinkedList<BasicBlock> Blocks { get; }
public BasicBlock[] PostOrderBlocks { get; }
public int[] PostOrderMap { get; }
public ControlFlowGraph(BasicBlock entry, LinkedList<BasicBlock> blocks)
{
Entry = entry;
Blocks = blocks;
RemoveUnreachableBlocks(blocks);
HashSet<BasicBlock> visited = new HashSet<BasicBlock>();
Stack<BasicBlock> blockStack = new Stack<BasicBlock>();
PostOrderBlocks = new BasicBlock[blocks.Count];
PostOrderMap = new int[blocks.Count];
visited.Add(entry);
blockStack.Push(entry);
int index = 0;
while (blockStack.TryPop(out BasicBlock block))
{
if (block.Next != null && visited.Add(block.Next))
{
blockStack.Push(block);
blockStack.Push(block.Next);
}
else if (block.Branch != null && visited.Add(block.Branch))
{
blockStack.Push(block);
blockStack.Push(block.Branch);
}
else
{
PostOrderMap[block.Index] = index;
PostOrderBlocks[index++] = block;
}
}
}
private void RemoveUnreachableBlocks(LinkedList<BasicBlock> blocks)
{
HashSet<BasicBlock> visited = new HashSet<BasicBlock>();
Queue<BasicBlock> workQueue = new Queue<BasicBlock>();
visited.Add(Entry);
workQueue.Enqueue(Entry);
while (workQueue.TryDequeue(out BasicBlock block))
{
Debug.Assert(block.Index != -1, "Invalid block index.");
if (block.Next != null && visited.Add(block.Next))
{
workQueue.Enqueue(block.Next);
}
if (block.Branch != null && visited.Add(block.Branch))
{
workQueue.Enqueue(block.Branch);
}
}
if (visited.Count < blocks.Count)
{
// Remove unreachable blocks and renumber.
int index = 0;
for (LinkedListNode<BasicBlock> node = blocks.First; node != null;)
{
LinkedListNode<BasicBlock> nextNode = node.Next;
BasicBlock block = node.Value;
if (!visited.Contains(block))
{
block.Next = null;
block.Branch = null;
blocks.Remove(node);
}
else
{
block.Index = index++;
}
node = nextNode;
}
}
}
public BasicBlock SplitEdge(BasicBlock predecessor, BasicBlock successor)
{
BasicBlock splitBlock = new BasicBlock(Blocks.Count);
if (predecessor.Next == successor)
{
predecessor.Next = splitBlock;
}
if (predecessor.Branch == successor)
{
predecessor.Branch = splitBlock;
}
if (splitBlock.Predecessors.Count == 0)
{
throw new ArgumentException("Predecessor and successor are not connected.");
}
// Insert the new block on the list of blocks.
BasicBlock succPrev = successor.Node.Previous?.Value;
if (succPrev != null && succPrev != predecessor && succPrev.Next == successor)
{
// Can't insert after the predecessor or before the successor.
// Here, we insert it before the successor by also spliting another
// edge (the one between the block before "successor" and "successor").
BasicBlock splitBlock2 = new BasicBlock(splitBlock.Index + 1);
succPrev.Next = splitBlock2;
splitBlock2.Branch = successor;
splitBlock2.Operations.AddLast(new Operation(Instruction.Branch, null));
Blocks.AddBefore(successor.Node, splitBlock2);
}
splitBlock.Next = successor;
Blocks.AddBefore(successor.Node, splitBlock);
return splitBlock;
}
}
}