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* GPU: Swap bindings array instead of copying Reduces work on UpdateShaderState. Now the cost is a few reference moves for arrays, rather than copying data. Downside: bindings arrays are no longer readonly. * Micro optimisation * Add missing docs * Address Feedback
220 lines
8.9 KiB
C#
220 lines
8.9 KiB
C#
using Ryujinx.Graphics.Device;
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using Ryujinx.Graphics.GAL;
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using Ryujinx.Graphics.Gpu.Engine.InlineToMemory;
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using Ryujinx.Graphics.Gpu.Engine.Threed;
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using Ryujinx.Graphics.Gpu.Engine.Types;
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using Ryujinx.Graphics.Gpu.Image;
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using Ryujinx.Graphics.Gpu.Shader;
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using Ryujinx.Graphics.Shader;
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using System;
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using System.Collections.Generic;
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using System.Runtime.CompilerServices;
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namespace Ryujinx.Graphics.Gpu.Engine.Compute
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{
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/// <summary>
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/// Represents a compute engine class.
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/// </summary>
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class ComputeClass : IDeviceState
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{
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private readonly GpuContext _context;
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private readonly GpuChannel _channel;
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private readonly ThreedClass _3dEngine;
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private readonly DeviceState<ComputeClassState> _state;
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private readonly InlineToMemoryClass _i2mClass;
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/// <summary>
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/// Creates a new instance of the compute engine class.
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/// </summary>
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/// <param name="context">GPU context</param>
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/// <param name="channel">GPU channel</param>
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/// <param name="threedEngine">3D engine</param>
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public ComputeClass(GpuContext context, GpuChannel channel, ThreedClass threedEngine)
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{
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_context = context;
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_channel = channel;
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_3dEngine = threedEngine;
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_state = new DeviceState<ComputeClassState>(new Dictionary<string, RwCallback>
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{
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{ nameof(ComputeClassState.LaunchDma), new RwCallback(LaunchDma, null) },
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{ nameof(ComputeClassState.LoadInlineData), new RwCallback(LoadInlineData, null) },
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{ nameof(ComputeClassState.SendSignalingPcasB), new RwCallback(SendSignalingPcasB, null) }
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});
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_i2mClass = new InlineToMemoryClass(context, channel, initializeState: false);
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}
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/// <summary>
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/// Reads data from the class registers.
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/// </summary>
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/// <param name="offset">Register byte offset</param>
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/// <returns>Data at the specified offset</returns>
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public int Read(int offset) => _state.Read(offset);
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/// <summary>
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/// Writes data to the class registers.
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/// </summary>
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/// <param name="offset">Register byte offset</param>
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/// <param name="data">Data to be written</param>
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public void Write(int offset, int data) => _state.Write(offset, data);
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/// <summary>
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/// Launches the Inline-to-Memory DMA copy operation.
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/// </summary>
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/// <param name="argument">Method call argument</param>
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private void LaunchDma(int argument)
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{
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_i2mClass.LaunchDma(ref Unsafe.As<ComputeClassState, InlineToMemoryClassState>(ref _state.State), argument);
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}
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/// <summary>
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/// Pushes a block of data to the Inline-to-Memory engine.
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/// </summary>
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/// <param name="data">Data to push</param>
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public void LoadInlineData(ReadOnlySpan<int> data)
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{
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_i2mClass.LoadInlineData(data);
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}
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/// <summary>
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/// Pushes a word of data to the Inline-to-Memory engine.
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/// </summary>
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/// <param name="argument">Method call argument</param>
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private void LoadInlineData(int argument)
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{
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_i2mClass.LoadInlineData(argument);
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}
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/// <summary>
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/// Performs the compute dispatch operation.
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/// </summary>
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/// <param name="argument">Method call argument</param>
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private void SendSignalingPcasB(int argument)
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{
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var memoryManager = _channel.MemoryManager;
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// Since we're going to change the state, make sure any pending instanced draws are done.
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_3dEngine.PerformDeferredDraws();
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// Make sure all pending uniform buffer data is written to memory.
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_3dEngine.FlushUboDirty();
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uint qmdAddress = _state.State.SendPcasA;
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var qmd = _channel.MemoryManager.Read<ComputeQmd>((ulong)qmdAddress << 8);
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ulong shaderGpuVa = ((ulong)_state.State.SetProgramRegionAAddressUpper << 32) | _state.State.SetProgramRegionB;
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shaderGpuVa += (uint)qmd.ProgramOffset;
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int localMemorySize = qmd.ShaderLocalMemoryLowSize + qmd.ShaderLocalMemoryHighSize;
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int sharedMemorySize = Math.Min(qmd.SharedMemorySize, _context.Capabilities.MaximumComputeSharedMemorySize);
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for (int index = 0; index < Constants.TotalCpUniformBuffers; index++)
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{
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if (!qmd.ConstantBufferValid(index))
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{
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continue;
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}
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ulong gpuVa = (uint)qmd.ConstantBufferAddrLower(index) | (ulong)qmd.ConstantBufferAddrUpper(index) << 32;
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ulong size = (ulong)qmd.ConstantBufferSize(index);
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_channel.BufferManager.SetComputeUniformBuffer(index, gpuVa, size);
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}
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ulong samplerPoolGpuVa = ((ulong)_state.State.SetTexSamplerPoolAOffsetUpper << 32) | _state.State.SetTexSamplerPoolB;
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ulong texturePoolGpuVa = ((ulong)_state.State.SetTexHeaderPoolAOffsetUpper << 32) | _state.State.SetTexHeaderPoolB;
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GpuChannelPoolState poolState = new GpuChannelPoolState(
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texturePoolGpuVa,
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_state.State.SetTexHeaderPoolCMaximumIndex,
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_state.State.SetBindlessTextureConstantBufferSlotSelect);
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GpuChannelComputeState computeState = new GpuChannelComputeState(
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qmd.CtaThreadDimension0,
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qmd.CtaThreadDimension1,
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qmd.CtaThreadDimension2,
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localMemorySize,
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sharedMemorySize,
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_channel.BufferManager.HasUnalignedStorageBuffers);
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CachedShaderProgram cs = memoryManager.Physical.ShaderCache.GetComputeShader(_channel, poolState, computeState, shaderGpuVa);
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_context.Renderer.Pipeline.SetProgram(cs.HostProgram);
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_channel.TextureManager.SetComputeSamplerPool(samplerPoolGpuVa, _state.State.SetTexSamplerPoolCMaximumIndex, qmd.SamplerIndex);
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_channel.TextureManager.SetComputeTexturePool(texturePoolGpuVa, _state.State.SetTexHeaderPoolCMaximumIndex);
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_channel.TextureManager.SetComputeTextureBufferIndex(_state.State.SetBindlessTextureConstantBufferSlotSelect);
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ShaderProgramInfo info = cs.Shaders[0].Info;
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bool hasUnaligned = _channel.BufferManager.HasUnalignedStorageBuffers;
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for (int index = 0; index < info.SBuffers.Count; index++)
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{
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BufferDescriptor sb = info.SBuffers[index];
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ulong sbDescAddress = _channel.BufferManager.GetComputeUniformBufferAddress(0);
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int sbDescOffset = 0x310 + sb.Slot * 0x10;
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sbDescAddress += (ulong)sbDescOffset;
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SbDescriptor sbDescriptor = _channel.MemoryManager.Physical.Read<SbDescriptor>(sbDescAddress);
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_channel.BufferManager.SetComputeStorageBuffer(sb.Slot, sbDescriptor.PackAddress(), (uint)sbDescriptor.Size, sb.Flags);
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}
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if ((_channel.BufferManager.HasUnalignedStorageBuffers) != hasUnaligned)
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{
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// Refetch the shader, as assumptions about storage buffer alignment have changed.
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cs = memoryManager.Physical.ShaderCache.GetComputeShader(_channel, poolState, computeState, shaderGpuVa);
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_context.Renderer.Pipeline.SetProgram(cs.HostProgram);
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info = cs.Shaders[0].Info;
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}
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for (int index = 0; index < info.CBuffers.Count; index++)
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{
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BufferDescriptor cb = info.CBuffers[index];
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// NVN uses the "hardware" constant buffer for anything that is less than 8,
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// and those are already bound above.
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// Anything greater than or equal to 8 uses the emulated constant buffers.
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// They are emulated using global memory loads.
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if (cb.Slot < 8)
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{
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continue;
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}
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ulong cbDescAddress = _channel.BufferManager.GetComputeUniformBufferAddress(0);
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int cbDescOffset = 0x260 + (cb.Slot - 8) * 0x10;
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cbDescAddress += (ulong)cbDescOffset;
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SbDescriptor cbDescriptor = _channel.MemoryManager.Physical.Read<SbDescriptor>(cbDescAddress);
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_channel.BufferManager.SetComputeUniformBuffer(cb.Slot, cbDescriptor.PackAddress(), (uint)cbDescriptor.Size);
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}
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_channel.BufferManager.SetComputeBufferBindings(cs.Bindings);
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_channel.TextureManager.SetComputeBindings(cs.Bindings);
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// Should never return false for mismatching spec state, since the shader was fetched above.
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_channel.TextureManager.CommitComputeBindings(cs.SpecializationState);
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_channel.BufferManager.CommitComputeBindings();
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_context.Renderer.Pipeline.DispatchCompute(qmd.CtaRasterWidth, qmd.CtaRasterHeight, qmd.CtaRasterDepth);
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_3dEngine.ForceShaderUpdate();
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}
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}
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}
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