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* Initial intrinsics support * Update tests to work with the new Vector128 type and intrinsics * Drop SSE4.1 requirement * Fix copy-paste mistake
170 lines
4.5 KiB
C#
170 lines
4.5 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics.X86;
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void And_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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{
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EmitSse2Call(Context, nameof(Sse2.And));
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}
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else
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{
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EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.And));
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}
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}
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public static void Bic_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.And);
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});
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}
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public static void Bic_Vi(AILEmitterCtx Context)
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{
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EmitVectorImmBinaryOp(Context, () =>
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{
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.And);
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});
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}
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public static void Bif_V(AILEmitterCtx Context)
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{
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EmitBitBif(Context, true);
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}
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public static void Bit_V(AILEmitterCtx Context)
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{
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EmitBitBif(Context, false);
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}
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public static void EmitBitBif(AILEmitterCtx Context, bool NotRm)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
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Context.Emit(OpCodes.Xor);
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EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size);
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if (NotRm)
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{
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Context.Emit(OpCodes.Not);
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}
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Context.Emit(OpCodes.And);
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EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
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Context.Emit(OpCodes.Xor);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Bsl_V(AILEmitterCtx Context)
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{
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EmitVectorTernaryOpZx(Context, () =>
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{
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Context.EmitSttmp();
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Context.EmitLdtmp();
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Context.Emit(OpCodes.Xor);
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Context.Emit(OpCodes.And);
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Context.EmitLdtmp();
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Context.Emit(OpCodes.Xor);
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});
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}
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public static void Eor_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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{
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EmitSse2Call(Context, nameof(Sse2.Xor));
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}
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else
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{
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EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Xor));
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}
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}
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public static void Not_V(AILEmitterCtx Context)
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{
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EmitVectorUnaryOpZx(Context, () => Context.Emit(OpCodes.Not));
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}
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public static void Orn_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Not);
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Context.Emit(OpCodes.Or);
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});
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}
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public static void Orr_V(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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{
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EmitSse2Call(Context, nameof(Sse2.Or));
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}
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else
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{
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EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Or));
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}
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}
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public static void Orr_Vi(AILEmitterCtx Context)
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{
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EmitVectorImmBinaryOp(Context, () => Context.Emit(OpCodes.Or));
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}
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public static void Rev64_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int RevIndex = Elems - 1;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, RevIndex--, Op.Size);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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}
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}
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