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https://github.com/Ryujinx/Ryujinx.git
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* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
156 lines
4.9 KiB
C#
156 lines
4.9 KiB
C#
using System;
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using System.Runtime.CompilerServices;
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using System.Runtime.InteropServices;
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namespace ARMeilleure.Memory
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{
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static class MemoryManagementWindows
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{
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[Flags]
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private enum AllocationType : uint
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{
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Commit = 0x1000,
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Reserve = 0x2000,
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Decommit = 0x4000,
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Release = 0x8000,
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Reset = 0x80000,
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Physical = 0x400000,
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TopDown = 0x100000,
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WriteWatch = 0x200000,
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LargePages = 0x20000000
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}
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[Flags]
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private enum MemoryProtection : uint
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{
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NoAccess = 0x01,
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ReadOnly = 0x02,
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ReadWrite = 0x04,
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WriteCopy = 0x08,
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Execute = 0x10,
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ExecuteRead = 0x20,
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ExecuteReadWrite = 0x40,
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ExecuteWriteCopy = 0x80,
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GuardModifierflag = 0x100,
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NoCacheModifierflag = 0x200,
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WriteCombineModifierflag = 0x400
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}
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private enum WriteWatchFlags : uint
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{
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None = 0,
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Reset = 1
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}
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[DllImport("kernel32.dll")]
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private static extern IntPtr VirtualAlloc(
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IntPtr lpAddress,
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IntPtr dwSize,
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AllocationType flAllocationType,
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MemoryProtection flProtect);
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[DllImport("kernel32.dll")]
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private static extern bool VirtualProtect(
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IntPtr lpAddress,
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IntPtr dwSize,
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MemoryProtection flNewProtect,
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out MemoryProtection lpflOldProtect);
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[DllImport("kernel32.dll")]
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private static extern bool VirtualFree(
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IntPtr lpAddress,
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IntPtr dwSize,
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AllocationType dwFreeType);
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[DllImport("kernel32.dll")]
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private static extern int GetWriteWatch(
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WriteWatchFlags dwFlags,
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IntPtr lpBaseAddress,
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IntPtr dwRegionSize,
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IntPtr[] lpAddresses,
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ref ulong lpdwCount,
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out uint lpdwGranularity);
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public static IntPtr Allocate(IntPtr size)
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{
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const AllocationType flags =
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AllocationType.Reserve |
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AllocationType.Commit;
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IntPtr ptr = VirtualAlloc(IntPtr.Zero, size, flags, MemoryProtection.ReadWrite);
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if (ptr == IntPtr.Zero)
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{
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throw new OutOfMemoryException();
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}
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return ptr;
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}
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public static IntPtr AllocateWriteTracked(IntPtr size)
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{
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const AllocationType flags =
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AllocationType.Reserve |
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AllocationType.Commit |
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AllocationType.WriteWatch;
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IntPtr ptr = VirtualAlloc(IntPtr.Zero, size, flags, MemoryProtection.ReadWrite);
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if (ptr == IntPtr.Zero)
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{
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throw new OutOfMemoryException();
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}
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return ptr;
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}
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public static bool Reprotect(IntPtr address, IntPtr size, Memory.MemoryProtection protection)
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{
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MemoryProtection prot = GetProtection(protection);
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return VirtualProtect(address, size, prot, out _);
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}
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private static MemoryProtection GetProtection(Memory.MemoryProtection protection)
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{
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switch (protection)
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{
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case Memory.MemoryProtection.None: return MemoryProtection.NoAccess;
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case Memory.MemoryProtection.Read: return MemoryProtection.ReadOnly;
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case Memory.MemoryProtection.ReadAndWrite: return MemoryProtection.ReadWrite;
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case Memory.MemoryProtection.ReadAndExecute: return MemoryProtection.ExecuteRead;
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case Memory.MemoryProtection.ReadWriteExecute: return MemoryProtection.ExecuteReadWrite;
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case Memory.MemoryProtection.Execute: return MemoryProtection.Execute;
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default: throw new ArgumentException($"Invalid permission \"{protection}\".");
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}
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}
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public static bool Free(IntPtr address)
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{
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return VirtualFree(address, IntPtr.Zero, AllocationType.Release);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static bool GetModifiedPages(
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IntPtr address,
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IntPtr size,
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IntPtr[] addresses,
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out ulong count)
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{
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ulong pagesCount = (ulong)addresses.Length;
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int result = GetWriteWatch(
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WriteWatchFlags.Reset,
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address,
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size,
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addresses,
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ref pagesCount,
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out uint granularity);
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count = pagesCount;
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return result == 0;
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}
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}
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} |