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* Implement VMAD shader instruction and improve InvocationInfo and ISBERD handling * Shader cache version bump * Fix typo
183 lines
6.4 KiB
C#
183 lines
6.4 KiB
C#
using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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public static void Vmnmx(EmitterContext context)
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{
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InstVmnmx op = context.GetOp<InstVmnmx>();
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Operand srcA = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcA), op.ASelect);
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Operand srcC = GetSrcReg(context, op.SrcC);
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Operand srcB;
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if (op.BVideo)
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{
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srcB = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcB), op.BSelect);
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}
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else
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{
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int imm = op.Imm16;
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if ((op.BSelect & VectorSelect.S8B0) != 0)
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{
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imm = (imm << 16) >> 16;
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}
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srcB = Const(imm);
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}
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Operand res;
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bool resSigned;
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if ((op.ASelect & VectorSelect.S8B0) != (op.BSelect & VectorSelect.S8B0))
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{
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// Signedness is different, but for max, result will always fit a U32,
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// since one of the inputs can't be negative, and the result is the one
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// with highest value. For min, it will always fit on a S32, since
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// one of the input can't be greater than INT_MAX and we want the lowest value.
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resSigned = !op.Mn;
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res = op.Mn ? context.IMaximumU32(srcA, srcB) : context.IMinimumS32(srcA, srcB);
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if ((op.ASelect & VectorSelect.S8B0) != 0)
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{
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Operand isBGtIntMax = context.ICompareLess(srcB, Const(0));
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res = context.ConditionalSelect(isBGtIntMax, srcB, res);
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}
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else
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{
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Operand isAGtIntMax = context.ICompareLess(srcA, Const(0));
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res = context.ConditionalSelect(isAGtIntMax, srcA, res);
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}
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}
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else
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{
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// Ra and Rb have the same signedness, so doesn't matter which one we test.
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resSigned = (op.ASelect & VectorSelect.S8B0) != 0;
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if (op.Mn)
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{
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res = resSigned
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? context.IMaximumS32(srcA, srcB)
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: context.IMaximumU32(srcA, srcB);
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}
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else
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{
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res = resSigned
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? context.IMinimumS32(srcA, srcB)
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: context.IMinimumU32(srcA, srcB);
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}
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}
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if (op.Sat)
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{
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if (op.DFormat && !resSigned)
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{
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res = context.IMinimumU32(res, Const(int.MaxValue));
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}
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else if (!op.DFormat && resSigned)
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{
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res = context.IMaximumS32(res, Const(0));
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}
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}
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switch (op.VideoOp)
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{
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case VideoOp.Acc:
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res = context.IAdd(res, srcC);
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break;
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case VideoOp.Max:
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res = op.DFormat ? context.IMaximumS32(res, srcC) : context.IMaximumU32(res, srcC);
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break;
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case VideoOp.Min:
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res = op.DFormat ? context.IMinimumS32(res, srcC) : context.IMinimumU32(res, srcC);
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break;
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case VideoOp.Mrg16h:
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res = context.BitfieldInsert(srcC, res, Const(16), Const(16));
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break;
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case VideoOp.Mrg16l:
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res = context.BitfieldInsert(srcC, res, Const(0), Const(16));
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break;
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case VideoOp.Mrg8b0:
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res = context.BitfieldInsert(srcC, res, Const(0), Const(8));
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break;
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case VideoOp.Mrg8b2:
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res = context.BitfieldInsert(srcC, res, Const(16), Const(8));
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break;
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}
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context.Copy(GetDest(op.Dest), res);
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}
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public static void Vsetp(EmitterContext context)
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{
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InstVsetp op = context.GetOp<InstVsetp>();
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Operand srcA = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcA), op.ASelect);
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Operand srcB;
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if (op.BVideo)
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{
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srcB = InstEmitAluHelper.Extend(context, GetSrcReg(context, op.SrcB), op.BSelect);
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}
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else
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{
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int imm = op.Imm16;
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if ((op.BSelect & VectorSelect.S8B0) != 0)
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{
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imm = (imm << 16) >> 16;
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}
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srcB = Const(imm);
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}
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Operand p0Res;
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bool signedA = (op.ASelect & VectorSelect.S8B0) != 0;
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bool signedB = (op.BSelect & VectorSelect.S8B0) != 0;
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if (signedA != signedB)
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{
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bool a32 = (op.ASelect & ~VectorSelect.S8B0) == VectorSelect.U32;
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bool b32 = (op.BSelect & ~VectorSelect.S8B0) == VectorSelect.U32;
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if (!a32 && !b32)
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{
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// Both values are extended small integer and can always fit in a S32, just do a signed comparison.
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p0Res = GetIntComparison(context, op.VComp, srcA, srcB, isSigned: true, extended: false);
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}
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else
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{
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// TODO: Mismatching sign case.
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p0Res = Const(0);
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}
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}
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else
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{
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// Sign matches, just do a regular comparison.
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p0Res = GetIntComparison(context, op.VComp, srcA, srcB, signedA, extended: false);
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}
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Operand p1Res = context.BitwiseNot(p0Res);
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Operand pred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
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p0Res = InstEmitAluHelper.GetPredLogicalOp(context, op.BoolOp, p0Res, pred);
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p1Res = InstEmitAluHelper.GetPredLogicalOp(context, op.BoolOp, p1Res, pred);
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context.Copy(Register(op.DestPred, RegisterType.Predicate), p0Res);
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context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
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}
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}
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} |