708 lines
No EOL
22 KiB
C#
708 lines
No EOL
22 KiB
C#
using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using System;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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public static void Bfe(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool isReverse = op.RawOpCode.Extract(40);
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bool isSigned = op.RawOpCode.Extract(48);
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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if (isReverse)
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{
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srcA = context.BitfieldReverse(srcA);
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}
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Operand position = context.BitwiseAnd(srcB, Const(0xff));
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Operand size = context.BitfieldExtractU32(srcB, Const(8), Const(8));
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Operand res = isSigned
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? context.BitfieldExtractS32(srcA, position, size)
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: context.BitfieldExtractU32(srcA, position, size);
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context.Copy(GetDest(context), res);
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// TODO: CC, X, corner cases
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}
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public static void Csetp(EmitterContext context)
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{
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OpCodePsetp op = (OpCodePsetp)context.CurrOp;
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// TODO: Implement that properly
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Operand p0Res = Const(IrConsts.True);
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Operand p1Res = context.BitwiseNot(p0Res);
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Operand pred = GetPredicate39(context);
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p0Res = GetPredLogicalOp(context, op.LogicalOp, p0Res, pred);
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p1Res = GetPredLogicalOp(context, op.LogicalOp, p1Res, pred);
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context.Copy(Register(op.Predicate3), p0Res);
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context.Copy(Register(op.Predicate0), p1Res);
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}
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public static void Iadd(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool negateA = false, negateB = false;
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if (!(op is OpCodeAluImm32))
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{
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negateB = op.RawOpCode.Extract(48);
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negateA = op.RawOpCode.Extract(49);
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}
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else
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{
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// TODO: Other IADD32I variant without the negate.
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negateA = op.RawOpCode.Extract(56);
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}
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Operand srcA = context.INegate(GetSrcA(context), negateA);
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Operand srcB = context.INegate(GetSrcB(context), negateB);
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Operand res = context.IAdd(srcA, srcB);
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bool isSubtraction = negateA || negateB;
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if (op.Extended)
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{
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// Add carry, or subtract borrow.
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res = context.IAdd(res, isSubtraction
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? context.BitwiseNot(GetCF(context))
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: context.BitwiseAnd(GetCF(context), Const(1)));
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}
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SetIaddFlags(context, res, srcA, srcB, op.SetCondCode, op.Extended, isSubtraction);
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context.Copy(GetDest(context), res);
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}
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public static void Iadd3(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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IntegerHalfPart partC = (IntegerHalfPart)op.RawOpCode.Extract(31, 2);
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IntegerHalfPart partB = (IntegerHalfPart)op.RawOpCode.Extract(33, 2);
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IntegerHalfPart partA = (IntegerHalfPart)op.RawOpCode.Extract(35, 2);
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IntegerShift mode = (IntegerShift)op.RawOpCode.Extract(37, 2);
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bool negateC = op.RawOpCode.Extract(49);
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bool negateB = op.RawOpCode.Extract(50);
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bool negateA = op.RawOpCode.Extract(51);
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Operand Extend(Operand src, IntegerHalfPart part)
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{
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if (!(op is OpCodeAluReg) || part == IntegerHalfPart.B32)
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{
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return src;
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}
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if (part == IntegerHalfPart.H0)
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{
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return context.BitwiseAnd(src, Const(0xffff));
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}
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else if (part == IntegerHalfPart.H1)
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{
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return context.ShiftRightU32(src, Const(16));
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}
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else
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{
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// TODO: Warning.
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}
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return src;
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}
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Operand srcA = context.INegate(Extend(GetSrcA(context), partA), negateA);
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Operand srcB = context.INegate(Extend(GetSrcB(context), partB), negateB);
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Operand srcC = context.INegate(Extend(GetSrcC(context), partC), negateC);
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Operand res = context.IAdd(srcA, srcB);
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if (op is OpCodeAluReg && mode != IntegerShift.NoShift)
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{
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if (mode == IntegerShift.ShiftLeft)
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{
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res = context.ShiftLeft(res, Const(16));
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}
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else if (mode == IntegerShift.ShiftRight)
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{
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res = context.ShiftRightU32(res, Const(16));
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}
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else
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{
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// TODO: Warning.
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}
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}
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res = context.IAdd(res, srcC);
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context.Copy(GetDest(context), res);
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// TODO: CC, X, corner cases
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}
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public static void Imnmx(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool isSignedInt = op.RawOpCode.Extract(48);
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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Operand resMin = isSignedInt
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? context.IMinimumS32(srcA, srcB)
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: context.IMinimumU32(srcA, srcB);
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Operand resMax = isSignedInt
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? context.IMaximumS32(srcA, srcB)
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: context.IMaximumU32(srcA, srcB);
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Operand pred = GetPredicate39(context);
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Operand dest = GetDest(context);
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context.Copy(dest, context.ConditionalSelect(pred, resMin, resMax));
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SetZnFlags(context, dest, op.SetCondCode);
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// TODO: X flags.
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}
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public static void Iscadd(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool negateA = false, negateB = false;
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if (!(op is OpCodeAluImm32))
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{
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negateB = op.RawOpCode.Extract(48);
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negateA = op.RawOpCode.Extract(49);
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}
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int shift = op is OpCodeAluImm32
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? op.RawOpCode.Extract(53, 5)
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: op.RawOpCode.Extract(39, 5);
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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srcA = context.ShiftLeft(srcA, Const(shift));
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srcA = context.INegate(srcA, negateA);
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srcB = context.INegate(srcB, negateB);
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Operand res = context.IAdd(srcA, srcB);
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context.Copy(GetDest(context), res);
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// TODO: CC, X
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}
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public static void Iset(EmitterContext context)
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{
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OpCodeSet op = (OpCodeSet)context.CurrOp;
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bool boolFloat = op.RawOpCode.Extract(44);
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bool isSigned = op.RawOpCode.Extract(48);
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IntegerCondition cmpOp = (IntegerCondition)op.RawOpCode.Extract(49, 3);
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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Operand res = GetIntComparison(context, cmpOp, srcA, srcB, isSigned);
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Operand pred = GetPredicate39(context);
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res = GetPredLogicalOp(context, op.LogicalOp, res, pred);
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Operand dest = GetDest(context);
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if (boolFloat)
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{
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context.Copy(dest, context.ConditionalSelect(res, ConstF(1), Const(0)));
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}
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else
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{
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context.Copy(dest, res);
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}
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// TODO: CC, X
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}
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public static void Isetp(EmitterContext context)
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{
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OpCodeSet op = (OpCodeSet)context.CurrOp;
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bool isSigned = op.RawOpCode.Extract(48);
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IntegerCondition cmpOp = (IntegerCondition)op.RawOpCode.Extract(49, 3);
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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Operand p0Res = GetIntComparison(context, cmpOp, srcA, srcB, isSigned);
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Operand p1Res = context.BitwiseNot(p0Res);
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Operand pred = GetPredicate39(context);
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p0Res = GetPredLogicalOp(context, op.LogicalOp, p0Res, pred);
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p1Res = GetPredLogicalOp(context, op.LogicalOp, p1Res, pred);
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context.Copy(Register(op.Predicate3), p0Res);
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context.Copy(Register(op.Predicate0), p1Res);
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}
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public static void Lop(EmitterContext context)
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{
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IOpCodeLop op = (IOpCodeLop)context.CurrOp;
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Operand srcA = context.BitwiseNot(GetSrcA(context), op.InvertA);
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Operand srcB = context.BitwiseNot(GetSrcB(context), op.InvertB);
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Operand res = srcB;
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switch (op.LogicalOp)
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{
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case LogicalOperation.And: res = context.BitwiseAnd (srcA, srcB); break;
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case LogicalOperation.Or: res = context.BitwiseOr (srcA, srcB); break;
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case LogicalOperation.ExclusiveOr: res = context.BitwiseExclusiveOr(srcA, srcB); break;
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}
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EmitLopPredWrite(context, op, res);
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Operand dest = GetDest(context);
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context.Copy(dest, res);
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SetZnFlags(context, dest, op.SetCondCode, op.Extended);
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}
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public static void Lop3(EmitterContext context)
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{
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IOpCodeLop op = (IOpCodeLop)context.CurrOp;
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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Operand srcC = GetSrcC(context);
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bool regVariant = op is OpCodeLopReg;
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int truthTable = regVariant
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? op.RawOpCode.Extract(28, 8)
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: op.RawOpCode.Extract(48, 8);
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Operand res = Lop3Expression.GetFromTruthTable(context, srcA, srcB, srcC, truthTable);
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if (regVariant)
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{
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EmitLopPredWrite(context, op, res);
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}
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Operand dest = GetDest(context);
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context.Copy(dest, res);
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SetZnFlags(context, dest, op.SetCondCode, op.Extended);
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}
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public static void Psetp(EmitterContext context)
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{
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OpCodePsetp op = (OpCodePsetp)context.CurrOp;
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bool invertA = op.RawOpCode.Extract(15);
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bool invertB = op.RawOpCode.Extract(32);
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Operand srcA = context.BitwiseNot(Register(op.Predicate12), invertA);
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Operand srcB = context.BitwiseNot(Register(op.Predicate29), invertB);
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Operand p0Res = GetPredLogicalOp(context, op.LogicalOpAB, srcA, srcB);
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Operand p1Res = context.BitwiseNot(p0Res);
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Operand pred = GetPredicate39(context);
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p0Res = GetPredLogicalOp(context, op.LogicalOp, p0Res, pred);
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p1Res = GetPredLogicalOp(context, op.LogicalOp, p1Res, pred);
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context.Copy(Register(op.Predicate3), p0Res);
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context.Copy(Register(op.Predicate0), p1Res);
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}
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public static void Rro(EmitterContext context)
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{
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// This is the range reduction operator,
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// we translate it as a simple move, as it
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// should be always followed by a matching
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// MUFU instruction.
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool negateB = op.RawOpCode.Extract(45);
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bool absoluteB = op.RawOpCode.Extract(49);
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Operand srcB = GetSrcB(context);
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srcB = context.FPAbsNeg(srcB, absoluteB, negateB);
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context.Copy(GetDest(context), srcB);
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}
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public static void Shl(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool isMasked = op.RawOpCode.Extract(39);
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Operand srcB = GetSrcB(context);
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if (isMasked)
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{
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srcB = context.BitwiseAnd(srcB, Const(0x1f));
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}
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Operand res = context.ShiftLeft(GetSrcA(context), srcB);
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if (!isMasked)
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{
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// Clamped shift value.
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Operand isLessThan32 = context.ICompareLessUnsigned(srcB, Const(32));
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res = context.ConditionalSelect(isLessThan32, res, Const(0));
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}
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// TODO: X, CC
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context.Copy(GetDest(context), res);
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}
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public static void Shr(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool isMasked = op.RawOpCode.Extract(39);
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bool isReverse = op.RawOpCode.Extract(40);
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bool isSigned = op.RawOpCode.Extract(48);
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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if (isReverse)
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{
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srcA = context.BitfieldReverse(srcA);
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}
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if (isMasked)
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{
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srcB = context.BitwiseAnd(srcB, Const(0x1f));
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}
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Operand res = isSigned
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? context.ShiftRightS32(srcA, srcB)
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: context.ShiftRightU32(srcA, srcB);
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if (!isMasked)
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{
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// Clamped shift value.
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Operand resShiftBy32;
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if (isSigned)
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{
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resShiftBy32 = context.ShiftRightS32(srcA, Const(31));
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}
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else
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{
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resShiftBy32 = Const(0);
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}
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Operand isLessThan32 = context.ICompareLessUnsigned(srcB, Const(32));
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res = context.ConditionalSelect(isLessThan32, res, resShiftBy32);
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}
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// TODO: X, CC
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context.Copy(GetDest(context), res);
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}
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public static void Xmad(EmitterContext context)
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{
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OpCodeAlu op = (OpCodeAlu)context.CurrOp;
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bool signedA = context.CurrOp.RawOpCode.Extract(48);
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bool signedB = context.CurrOp.RawOpCode.Extract(49);
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bool highA = context.CurrOp.RawOpCode.Extract(53);
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bool highB = false;
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XmadCMode mode;
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if (op is OpCodeAluReg)
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{
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highB = context.CurrOp.RawOpCode.Extract(35);
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mode = (XmadCMode)context.CurrOp.RawOpCode.Extract(50, 3);
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}
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else
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{
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mode = (XmadCMode)context.CurrOp.RawOpCode.Extract(50, 2);
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if (!(op is OpCodeAluImm))
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{
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highB = context.CurrOp.RawOpCode.Extract(52);
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}
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}
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Operand srcA = GetSrcA(context);
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Operand srcB = GetSrcB(context);
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Operand srcC = GetSrcC(context);
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// XMAD immediates are 16-bits unsigned integers.
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if (srcB.Type == OperandType.Constant)
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{
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srcB = Const(srcB.Value & 0xffff);
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}
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Operand Extend16To32(Operand src, bool high, bool signed)
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{
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if (signed && high)
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{
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return context.ShiftRightS32(src, Const(16));
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}
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else if (signed)
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{
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return context.BitfieldExtractS32(src, Const(0), Const(16));
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}
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else if (high)
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{
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return context.ShiftRightU32(src, Const(16));
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}
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else
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{
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return context.BitwiseAnd(src, Const(0xffff));
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}
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}
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srcA = Extend16To32(srcA, highA, signedA);
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srcB = Extend16To32(srcB, highB, signedB);
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bool productShiftLeft = false;
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bool merge = false;
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if (!(op is OpCodeAluRegCbuf))
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{
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productShiftLeft = context.CurrOp.RawOpCode.Extract(36);
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merge = context.CurrOp.RawOpCode.Extract(37);
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}
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bool extended;
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if ((op is OpCodeAluReg) || (op is OpCodeAluImm))
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{
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extended = context.CurrOp.RawOpCode.Extract(38);
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}
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else
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{
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extended = context.CurrOp.RawOpCode.Extract(54);
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}
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Operand res = context.IMultiply(srcA, srcB);
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if (productShiftLeft)
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{
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res = context.ShiftLeft(res, Const(16));
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}
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switch (mode)
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{
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case XmadCMode.Cfull: break;
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case XmadCMode.Clo: srcC = Extend16To32(srcC, high: false, signed: false); break;
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case XmadCMode.Chi: srcC = Extend16To32(srcC, high: true, signed: false); break;
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case XmadCMode.Cbcc:
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{
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|
srcC = context.IAdd(srcC, context.ShiftLeft(GetSrcB(context), Const(16)));
|
|
|
|
break;
|
|
}
|
|
|
|
case XmadCMode.Csfu:
|
|
{
|
|
Operand signAdjustA = context.ShiftLeft(context.ShiftRightU32(srcA, Const(31)), Const(16));
|
|
Operand signAdjustB = context.ShiftLeft(context.ShiftRightU32(srcB, Const(31)), Const(16));
|
|
|
|
srcC = context.ISubtract(srcC, context.IAdd(signAdjustA, signAdjustB));
|
|
|
|
break;
|
|
}
|
|
|
|
default: /* TODO: Warning */ break;
|
|
}
|
|
|
|
Operand product = res;
|
|
|
|
if (extended)
|
|
{
|
|
// Add with carry.
|
|
res = context.IAdd(res, context.BitwiseAnd(GetCF(context), Const(1)));
|
|
}
|
|
else
|
|
{
|
|
// Add (no carry in).
|
|
res = context.IAdd(res, srcC);
|
|
}
|
|
|
|
SetIaddFlags(context, res, product, srcC, op.SetCondCode, extended);
|
|
|
|
if (merge)
|
|
{
|
|
res = context.BitwiseAnd(res, Const(0xffff));
|
|
res = context.BitwiseOr(res, context.ShiftLeft(GetSrcB(context), Const(16)));
|
|
}
|
|
|
|
context.Copy(GetDest(context), res);
|
|
}
|
|
|
|
private static Operand GetIntComparison(
|
|
EmitterContext context,
|
|
IntegerCondition cond,
|
|
Operand srcA,
|
|
Operand srcB,
|
|
bool isSigned)
|
|
{
|
|
Operand res;
|
|
|
|
if (cond == IntegerCondition.Always)
|
|
{
|
|
res = Const(IrConsts.True);
|
|
}
|
|
else if (cond == IntegerCondition.Never)
|
|
{
|
|
res = Const(IrConsts.False);
|
|
}
|
|
else
|
|
{
|
|
Instruction inst;
|
|
|
|
switch (cond)
|
|
{
|
|
case IntegerCondition.Less: inst = Instruction.CompareLessU32; break;
|
|
case IntegerCondition.Equal: inst = Instruction.CompareEqual; break;
|
|
case IntegerCondition.LessOrEqual: inst = Instruction.CompareLessOrEqualU32; break;
|
|
case IntegerCondition.Greater: inst = Instruction.CompareGreaterU32; break;
|
|
case IntegerCondition.NotEqual: inst = Instruction.CompareNotEqual; break;
|
|
case IntegerCondition.GreaterOrEqual: inst = Instruction.CompareGreaterOrEqualU32; break;
|
|
|
|
default: throw new InvalidOperationException($"Unexpected condition \"{cond}\".");
|
|
}
|
|
|
|
if (isSigned)
|
|
{
|
|
switch (cond)
|
|
{
|
|
case IntegerCondition.Less: inst = Instruction.CompareLess; break;
|
|
case IntegerCondition.LessOrEqual: inst = Instruction.CompareLessOrEqual; break;
|
|
case IntegerCondition.Greater: inst = Instruction.CompareGreater; break;
|
|
case IntegerCondition.GreaterOrEqual: inst = Instruction.CompareGreaterOrEqual; break;
|
|
}
|
|
}
|
|
|
|
res = context.Add(inst, Local(), srcA, srcB);
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
private static void EmitLopPredWrite(EmitterContext context, IOpCodeLop op, Operand result)
|
|
{
|
|
if (op is OpCodeLop opLop && !opLop.Predicate48.IsPT)
|
|
{
|
|
Operand pRes;
|
|
|
|
if (opLop.CondOp == ConditionalOperation.False)
|
|
{
|
|
pRes = Const(IrConsts.False);
|
|
}
|
|
else if (opLop.CondOp == ConditionalOperation.True)
|
|
{
|
|
pRes = Const(IrConsts.True);
|
|
}
|
|
else if (opLop.CondOp == ConditionalOperation.Zero)
|
|
{
|
|
pRes = context.ICompareEqual(result, Const(0));
|
|
}
|
|
else /* if (opLop.CondOp == ConditionalOperation.NotZero) */
|
|
{
|
|
pRes = context.ICompareNotEqual(result, Const(0));
|
|
}
|
|
|
|
context.Copy(Register(opLop.Predicate48), pRes);
|
|
}
|
|
}
|
|
|
|
private static void SetIaddFlags(
|
|
EmitterContext context,
|
|
Operand res,
|
|
Operand srcA,
|
|
Operand srcB,
|
|
bool setCC,
|
|
bool extended,
|
|
bool isSubtraction = false)
|
|
{
|
|
if (!setCC)
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (!extended || isSubtraction)
|
|
{
|
|
// C = d < a
|
|
context.Copy(GetCF(context), context.ICompareLessUnsigned(res, srcA));
|
|
}
|
|
else
|
|
{
|
|
// C = (d == a && CIn) || d < a
|
|
Operand tempC0 = context.ICompareEqual (res, srcA);
|
|
Operand tempC1 = context.ICompareLessUnsigned(res, srcA);
|
|
|
|
tempC0 = context.BitwiseAnd(tempC0, GetCF(context));
|
|
|
|
context.Copy(GetCF(context), context.BitwiseOr(tempC0, tempC1));
|
|
}
|
|
|
|
// V = (d ^ a) & ~(a ^ b) < 0
|
|
Operand tempV0 = context.BitwiseExclusiveOr(res, srcA);
|
|
Operand tempV1 = context.BitwiseExclusiveOr(srcA, srcB);
|
|
|
|
tempV1 = context.BitwiseNot(tempV1);
|
|
|
|
Operand tempV = context.BitwiseAnd(tempV0, tempV1);
|
|
|
|
context.Copy(GetVF(context), context.ICompareLess(tempV, Const(0)));
|
|
|
|
SetZnFlags(context, res, setCC: true, extended: extended);
|
|
}
|
|
}
|
|
} |