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https://github.com/Ryujinx/Ryujinx.git
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184 lines
5.3 KiB
C#
184 lines
5.3 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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public static void Adr(ArmEmitterContext context)
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{
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OpCodeAdr op = (OpCodeAdr)context.CurrOp;
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SetIntOrZR(context, op.Rd, Const(op.Address + (ulong)op.Immediate));
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}
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public static void Adrp(ArmEmitterContext context)
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{
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OpCodeAdr op = (OpCodeAdr)context.CurrOp;
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ulong address = (op.Address & ~0xfffUL) + ((ulong)op.Immediate << 12);
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SetIntOrZR(context, op.Rd, Const(address));
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}
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public static void Ldr(ArmEmitterContext context) => EmitLdr(context, signed: false);
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public static void Ldrs(ArmEmitterContext context) => EmitLdr(context, signed: true);
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private static void EmitLdr(ArmEmitterContext context, bool signed)
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{
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OpCodeMem op = (OpCodeMem)context.CurrOp;
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Operand address = GetAddress(context);
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if (signed && op.Extend64)
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{
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EmitLoadSx64(context, address, op.Rt, op.Size);
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}
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else if (signed)
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{
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EmitLoadSx32(context, address, op.Rt, op.Size);
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}
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else
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{
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EmitLoadZx(context, address, op.Rt, op.Size);
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}
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EmitWBackIfNeeded(context, address);
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}
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public static void Ldr_Literal(ArmEmitterContext context)
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{
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IOpCodeLit op = (IOpCodeLit)context.CurrOp;
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if (op.Prefetch)
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{
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return;
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}
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if (op.Signed)
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{
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EmitLoadSx64(context, Const(op.Immediate), op.Rt, op.Size);
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}
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else
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{
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EmitLoadZx(context, Const(op.Immediate), op.Rt, op.Size);
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}
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}
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public static void Ldp(ArmEmitterContext context)
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{
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OpCodeMemPair op = (OpCodeMemPair)context.CurrOp;
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void EmitLoad(int rt, Operand ldAddr)
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{
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if (op.Extend64)
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{
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EmitLoadSx64(context, ldAddr, rt, op.Size);
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}
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else
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{
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EmitLoadZx(context, ldAddr, rt, op.Size);
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}
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}
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Operand address = GetAddress(context);
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Operand address2 = GetAddress(context, 1L << op.Size);
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EmitLoad(op.Rt, address);
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EmitLoad(op.Rt2, address2);
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EmitWBackIfNeeded(context, address);
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}
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public static void Str(ArmEmitterContext context)
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{
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OpCodeMem op = (OpCodeMem)context.CurrOp;
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Operand address = GetAddress(context);
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EmitStore(context, address, op.Rt, op.Size);
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EmitWBackIfNeeded(context, address);
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}
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public static void Stp(ArmEmitterContext context)
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{
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OpCodeMemPair op = (OpCodeMemPair)context.CurrOp;
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Operand address = GetAddress(context);
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Operand address2 = GetAddress(context, 1L << op.Size);
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EmitStore(context, address, op.Rt, op.Size);
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EmitStore(context, address2, op.Rt2, op.Size);
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EmitWBackIfNeeded(context, address);
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}
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private static Operand GetAddress(ArmEmitterContext context, long addend = 0)
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{
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Operand address = default;
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switch (context.CurrOp)
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{
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case OpCodeMemImm op:
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{
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address = context.Copy(GetIntOrSP(context, op.Rn));
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// Pre-indexing.
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if (!op.PostIdx)
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{
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address = context.Add(address, Const(op.Immediate + addend));
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}
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else if (addend != 0)
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{
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address = context.Add(address, Const(addend));
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}
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break;
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}
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case OpCodeMemReg op:
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{
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Operand n = GetIntOrSP(context, op.Rn);
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Operand m = GetExtendedM(context, op.Rm, op.IntType);
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if (op.Shift)
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{
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m = context.ShiftLeft(m, Const(op.Size));
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}
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address = context.Add(n, m);
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if (addend != 0)
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{
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address = context.Add(address, Const(addend));
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}
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break;
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}
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}
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return address;
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}
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private static void EmitWBackIfNeeded(ArmEmitterContext context, Operand address)
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{
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// Check whenever the current OpCode has post-indexed write back, if so write it.
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if (context.CurrOp is OpCodeMemImm op && op.WBack)
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{
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if (op.PostIdx)
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{
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address = context.Add(address, Const(op.Immediate));
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}
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SetIntOrSP(context, op.Rn, address);
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}
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}
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}
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} |