N-archive/citra
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Fix read-after-write in SMUAD, SMLAD, SMUSD, SMLSD

Browse source
This commit is contained in:
Jannik Vogel 2016-05-18 13:59:05 +02:00
parent 960297e577
commit 3a45eacb16
1 changed files with 8 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View file

@ -5527,28 +5527,32 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
// SMUAD and SMLAD // SMUAD and SMLAD
if (BIT(op2, 1) == 0) { if (BIT(op2, 1) == 0) {
RD = (product1 + product2); u32 rd_val = (product1 + product2);
if (inst_cream->Ra != 15) { if (inst_cream->Ra != 15) {
RD += cpu->Reg[inst_cream->Ra]; rd_val += cpu->Reg[inst_cream->Ra];
if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra])) if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra]))
cpu->Cpsr |= (1 << 27); cpu->Cpsr |= (1 << 27);
} }
RD = rd_val;
if (ARMul_AddOverflowQ(product1, product2)) if (ARMul_AddOverflowQ(product1, product2))
cpu->Cpsr |= (1 << 27); cpu->Cpsr |= (1 << 27);
} }
// SMUSD and SMLSD // SMUSD and SMLSD
else { else {
RD = (product1 - product2); u32 rd_val = (product1 - product2);
if (inst_cream->Ra != 15) { if (inst_cream->Ra != 15) {
RD += cpu->Reg[inst_cream->Ra]; rd_val += cpu->Reg[inst_cream->Ra];
if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra])) if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra]))
cpu->Cpsr |= (1 << 27); cpu->Cpsr |= (1 << 27);
} }
RD = rd_val;
} }
} }