N-archive/citra
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

hacked CPU interpreter to ignore branch on SVC instruction (as we are HLEing this...)

Browse source
This commit is contained in:
bunnei 2014-04-12 01:36:39 -04:00
parent cd7de52fea
commit 4d88318903
1 changed files with 6 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/core/arm/interpreter/arminit.cpp
View file

@ -530,9 +530,13 @@ ARMul_Abort (ARMul_State * state, ARMword vector)
isize); isize);
break; break;
case ARMul_SWIV: /* Software Interrupt */ case ARMul_SWIV: /* Software Interrupt */
SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, // Modified SETABORT that doesn't branch to a SVC vector as we are implementing this in HLE
// Instead of doing normal routine, backup R15 by one instruction (this is what PC will get
// set to, making it the next instruction after the SVC call), and skip setting the LR.
SETABORT_SKIPBRANCH (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
isize); isize);
break; state->Reg[15] -= 4;
return;
case ARMul_PrefetchAbortV: /* Prefetch Abort */ case ARMul_PrefetchAbortV: /* Prefetch Abort */
state->AbortAddr = 1; state->AbortAddr = 1;
SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,