From e7719a52cdc16c5fe6dc296a05c96f7de4aa9ffb Mon Sep 17 00:00:00 2001
From: Yuri Kunde Schlesner <yuriks@yuriks.net>
Date: Thu, 28 Aug 2014 15:17:09 -0300
Subject: [PATCH] Rename GPU::Regs::FramebufferFormat to PixelFormat

This name better represents what the enum does, and is less overloaded
in the context. (The whole register the enum is part of is also called
'format'.)
---
 src/core/hw/gpu.cpp | 10 +++++-----
 src/core/hw/gpu.h   |  8 ++++----
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp
index f1f3e7ab3..c91185751 100644
--- a/src/core/hw/gpu.cpp
+++ b/src/core/hw/gpu.cpp
@@ -90,7 +90,7 @@ inline void Write(u32 addr, const T data) {
                     } source_color = { 0, 0, 0, 0 };
 
                     switch (config.input_format) {
-                    case Regs::FramebufferFormat::RGBA8:
+                    case Regs::PixelFormat::RGBA8:
                     {
                         // TODO: Most likely got the component order messed up.
                         u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4;
@@ -107,7 +107,7 @@ inline void Write(u32 addr, const T data) {
                     }
 
                     switch (config.output_format) {
-                    /*case Regs::FramebufferFormat::RGBA8:
+                    /*case Regs::PixelFormat::RGBA8:
                     {
                         // TODO: Untested
                         u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4);
@@ -118,7 +118,7 @@ inline void Write(u32 addr, const T data) {
                         break;
                     }*/
 
-                    case Regs::FramebufferFormat::RGB8:
+                    case Regs::PixelFormat::RGB8:
                     {
                         // TODO: Most likely got the component order messed up.
                         u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3;
@@ -220,13 +220,13 @@ void Init() {
     framebuffer_top.width = 240;
     framebuffer_top.height = 400;
     framebuffer_top.stride = 3 * 240;
-    framebuffer_top.color_format = Regs::FramebufferFormat::RGB8;
+    framebuffer_top.color_format = Regs::PixelFormat::RGB8;
     framebuffer_top.active_fb = 0;
 
     framebuffer_sub.width = 240;
     framebuffer_sub.height = 320;
     framebuffer_sub.stride = 3 * 240;
-    framebuffer_sub.color_format = Regs::FramebufferFormat::RGB8;
+    framebuffer_sub.color_format = Regs::PixelFormat::RGB8;
     framebuffer_sub.active_fb = 0;
 
     NOTICE_LOG(GPU, "initialized OK");
diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h
index 7186bfa84..cf98127eb 100644
--- a/src/core/hw/gpu.h
+++ b/src/core/hw/gpu.h
@@ -56,7 +56,7 @@ struct Regs {
                   "Structure size and register block length don't match")
 #endif
 
-    enum class FramebufferFormat : u32 {
+    enum class PixelFormat : u32 {
         RGBA8  = 0,
         RGB8   = 1,
         RGB565 = 2,
@@ -84,8 +84,8 @@ struct Regs {
 
     INSERT_PADDING_WORDS(0x10b);
 
-    struct {
-        using Format = Regs::FramebufferFormat;
+    struct FramebufferConfig {
+        using Format = Regs::PixelFormat;
 
         union {
             u32 size;
@@ -130,7 +130,7 @@ struct Regs {
     INSERT_PADDING_WORDS(0x169);
 
     struct {
-        using Format = Regs::FramebufferFormat;
+        using Format = Regs::PixelFormat;
 
         u32 input_address;
         u32 output_address;