798 lines
28 KiB
C++
798 lines
28 KiB
C++
// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <smmintrin.h>
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#include "common/x64/abi.h"
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#include "common/x64/cpu_detect.h"
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#include "common/x64/emitter.h"
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#include "shader.h"
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#include "shader_jit_x64.h"
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namespace Pica {
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namespace Shader {
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using namespace Gen;
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typedef void (JitCompiler::*JitFunction)(Instruction instr);
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const JitFunction instr_table[64] = {
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&JitCompiler::Compile_ADD, // add
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&JitCompiler::Compile_DP3, // dp3
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&JitCompiler::Compile_DP4, // dp4
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&JitCompiler::Compile_DPH, // dph
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nullptr, // unknown
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&JitCompiler::Compile_EX2, // ex2
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&JitCompiler::Compile_LG2, // lg2
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nullptr, // unknown
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&JitCompiler::Compile_MUL, // mul
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&JitCompiler::Compile_SGE, // sge
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&JitCompiler::Compile_SLT, // slt
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&JitCompiler::Compile_FLR, // flr
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&JitCompiler::Compile_MAX, // max
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&JitCompiler::Compile_MIN, // min
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&JitCompiler::Compile_RCP, // rcp
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&JitCompiler::Compile_RSQ, // rsq
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nullptr, // unknown
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nullptr, // unknown
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&JitCompiler::Compile_MOVA, // mova
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&JitCompiler::Compile_MOV, // mov
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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&JitCompiler::Compile_DPH, // dphi
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nullptr, // unknown
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&JitCompiler::Compile_SGE, // sgei
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&JitCompiler::Compile_SLT, // slti
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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&JitCompiler::Compile_NOP, // nop
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&JitCompiler::Compile_END, // end
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nullptr, // break
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&JitCompiler::Compile_CALL, // call
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&JitCompiler::Compile_CALLC, // callc
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&JitCompiler::Compile_CALLU, // callu
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&JitCompiler::Compile_IF, // ifu
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&JitCompiler::Compile_IF, // ifc
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&JitCompiler::Compile_LOOP, // loop
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nullptr, // emit
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nullptr, // sete
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&JitCompiler::Compile_JMP, // jmpc
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&JitCompiler::Compile_JMP, // jmpu
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&JitCompiler::Compile_CMP, // cmp
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&JitCompiler::Compile_CMP, // cmp
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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};
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// The following is used to alias some commonly used registers. Generally, RAX-RDX and XMM0-XMM3 can
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// be used as scratch registers within a compiler function. The other registers have designated
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// purposes, as documented below:
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/// Pointer to the uniform memory
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static const X64Reg UNIFORMS = R9;
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/// The two 32-bit VS address offset registers set by the MOVA instruction
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static const X64Reg ADDROFFS_REG_0 = R10;
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static const X64Reg ADDROFFS_REG_1 = R11;
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/// VS loop count register
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static const X64Reg LOOPCOUNT_REG = R12;
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/// Current VS loop iteration number (we could probably use LOOPCOUNT_REG, but this quicker)
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static const X64Reg LOOPCOUNT = RSI;
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/// Number to increment LOOPCOUNT_REG by on each loop iteration
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static const X64Reg LOOPINC = RDI;
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/// Result of the previous CMP instruction for the X-component comparison
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static const X64Reg COND0 = R13;
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/// Result of the previous CMP instruction for the Y-component comparison
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static const X64Reg COND1 = R14;
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/// Pointer to the UnitState instance for the current VS unit
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static const X64Reg REGISTERS = R15;
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/// SIMD scratch register
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static const X64Reg SCRATCH = XMM0;
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/// Loaded with the first swizzled source register, otherwise can be used as a scratch register
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static const X64Reg SRC1 = XMM1;
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/// Loaded with the second swizzled source register, otherwise can be used as a scratch register
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static const X64Reg SRC2 = XMM2;
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/// Loaded with the third swizzled source register, otherwise can be used as a scratch register
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static const X64Reg SRC3 = XMM3;
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/// Additional scratch register
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static const X64Reg SCRATCH2 = XMM4;
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/// Constant vector of [1.0f, 1.0f, 1.0f, 1.0f], used to efficiently set a vector to one
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static const X64Reg ONE = XMM14;
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/// Constant vector of [-0.f, -0.f, -0.f, -0.f], used to efficiently negate a vector with XOR
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static const X64Reg NEGBIT = XMM15;
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/// Raw constant for the source register selector that indicates no swizzling is performed
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static const u8 NO_SRC_REG_SWIZZLE = 0x1b;
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/// Raw constant for the destination register enable mask that indicates all components are enabled
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static const u8 NO_DEST_REG_MASK = 0xf;
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/**
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* Loads and swizzles a source register into the specified XMM register.
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* @param instr VS instruction, used for determining how to load the source register
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* @param src_num Number indicating which source register to load (1 = src1, 2 = src2, 3 = src3)
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* @param src_reg SourceRegister object corresponding to the source register to load
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* @param dest Destination XMM register to store the loaded, swizzled source register
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*/
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void JitCompiler::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRegister src_reg, X64Reg dest) {
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X64Reg src_ptr;
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int src_offset;
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if (src_reg.GetRegisterType() == RegisterType::FloatUniform) {
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src_ptr = UNIFORMS;
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src_offset = src_reg.GetIndex() * sizeof(float24) * 4;
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} else {
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src_ptr = REGISTERS;
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src_offset = UnitState<false>::InputOffset(src_reg);
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}
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unsigned operand_desc_id;
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if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD ||
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instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI) {
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// The MAD and MADI instructions do not use the address offset registers, so loading the
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// source is a bit simpler here
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operand_desc_id = instr.mad.operand_desc_id;
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// Load the source
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MOVAPS(dest, MDisp(src_ptr, src_offset));
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} else {
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operand_desc_id = instr.common.operand_desc_id;
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const bool is_inverted = (0 != (instr.opcode.Value().GetInfo().subtype & OpCode::Info::SrcInversed));
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unsigned offset_src = is_inverted ? 2 : 1;
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if (src_num == offset_src && instr.common.address_register_index != 0) {
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switch (instr.common.address_register_index) {
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case 1: // address offset 1
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MOVAPS(dest, MComplex(src_ptr, ADDROFFS_REG_0, 1, src_offset));
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break;
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case 2: // address offset 2
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MOVAPS(dest, MComplex(src_ptr, ADDROFFS_REG_1, 1, src_offset));
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break;
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case 3: // adddress offet 3
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MOVAPS(dest, MComplex(src_ptr, LOOPCOUNT_REG, 1, src_offset));
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break;
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default:
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UNREACHABLE();
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break;
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}
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} else {
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// Load the source
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MOVAPS(dest, MDisp(src_ptr, src_offset));
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}
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}
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SwizzlePattern swiz = { g_state.vs.swizzle_data[operand_desc_id] };
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// Generate instructions for source register swizzling as needed
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u8 sel = swiz.GetRawSelector(src_num);
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if (sel != NO_SRC_REG_SWIZZLE) {
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// Selector component order needs to be reversed for the SHUFPS instruction
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sel = ((sel & 0xc0) >> 6) | ((sel & 3) << 6) | ((sel & 0xc) << 2) | ((sel & 0x30) >> 2);
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// Shuffle inputs for swizzle
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SHUFPS(dest, R(dest), sel);
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}
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// If the source register should be negated, flip the negative bit using XOR
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const bool negate[] = { swiz.negate_src1, swiz.negate_src2, swiz.negate_src3 };
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if (negate[src_num - 1]) {
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XORPS(dest, R(NEGBIT));
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}
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}
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void JitCompiler::Compile_DestEnable(Instruction instr,X64Reg src) {
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DestRegister dest;
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unsigned operand_desc_id;
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if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD ||
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instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI) {
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operand_desc_id = instr.mad.operand_desc_id;
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dest = instr.mad.dest.Value();
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} else {
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operand_desc_id = instr.common.operand_desc_id;
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dest = instr.common.dest.Value();
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}
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SwizzlePattern swiz = { g_state.vs.swizzle_data[operand_desc_id] };
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// If all components are enabled, write the result to the destination register
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if (swiz.dest_mask == NO_DEST_REG_MASK) {
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// Store dest back to memory
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MOVAPS(MDisp(REGISTERS, UnitState<false>::OutputOffset(dest)), src);
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} else {
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// Not all components are enabled, so mask the result when storing to the destination register...
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MOVAPS(SCRATCH, MDisp(REGISTERS, UnitState<false>::OutputOffset(dest)));
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if (Common::GetCPUCaps().sse4_1) {
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u8 mask = ((swiz.dest_mask & 1) << 3) | ((swiz.dest_mask & 8) >> 3) | ((swiz.dest_mask & 2) << 1) | ((swiz.dest_mask & 4) >> 1);
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BLENDPS(SCRATCH, R(src), mask);
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} else {
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MOVAPS(SCRATCH2, R(src));
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UNPCKHPS(SCRATCH2, R(SCRATCH)); // Unpack X/Y components of source and destination
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UNPCKLPS(SCRATCH, R(src)); // Unpack Z/W components of source and destination
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// Compute selector to selectively copy source components to destination for SHUFPS instruction
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u8 sel = ((swiz.DestComponentEnabled(0) ? 1 : 0) << 0) |
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((swiz.DestComponentEnabled(1) ? 3 : 2) << 2) |
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((swiz.DestComponentEnabled(2) ? 0 : 1) << 4) |
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((swiz.DestComponentEnabled(3) ? 2 : 3) << 6);
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SHUFPS(SCRATCH, R(SCRATCH2), sel);
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}
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// Store dest back to memory
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MOVAPS(MDisp(REGISTERS, UnitState<false>::OutputOffset(dest)), SCRATCH);
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}
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}
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void JitCompiler::Compile_EvaluateCondition(Instruction instr) {
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// Note: NXOR is used below to check for equality
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switch (instr.flow_control.op) {
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case Instruction::FlowControlType::Or:
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MOV(32, R(RAX), R(COND0));
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MOV(32, R(RBX), R(COND1));
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XOR(32, R(RAX), Imm32(instr.flow_control.refx.Value() ^ 1));
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XOR(32, R(RBX), Imm32(instr.flow_control.refy.Value() ^ 1));
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OR(32, R(RAX), R(RBX));
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break;
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case Instruction::FlowControlType::And:
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MOV(32, R(RAX), R(COND0));
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MOV(32, R(RBX), R(COND1));
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XOR(32, R(RAX), Imm32(instr.flow_control.refx.Value() ^ 1));
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XOR(32, R(RBX), Imm32(instr.flow_control.refy.Value() ^ 1));
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AND(32, R(RAX), R(RBX));
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break;
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case Instruction::FlowControlType::JustX:
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MOV(32, R(RAX), R(COND0));
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XOR(32, R(RAX), Imm32(instr.flow_control.refx.Value() ^ 1));
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break;
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case Instruction::FlowControlType::JustY:
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MOV(32, R(RAX), R(COND1));
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XOR(32, R(RAX), Imm32(instr.flow_control.refy.Value() ^ 1));
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break;
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}
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}
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void JitCompiler::Compile_UniformCondition(Instruction instr) {
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int offset = offsetof(decltype(g_state.vs.uniforms), b) + (instr.flow_control.bool_uniform_id * sizeof(bool));
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CMP(sizeof(bool) * 8, MDisp(UNIFORMS, offset), Imm8(0));
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}
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void JitCompiler::Compile_PushCallerSavedXMM() {
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#ifndef _WIN32
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SUB(64, R(RSP), Imm8(2 * 16));
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MOVUPS(MDisp(RSP, 16), ONE);
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MOVUPS(MDisp(RSP, 0), NEGBIT);
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#endif
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}
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void JitCompiler::Compile_PopCallerSavedXMM() {
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#ifndef _WIN32
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MOVUPS(NEGBIT, MDisp(RSP, 0));
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MOVUPS(ONE, MDisp(RSP, 16));
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ADD(64, R(RSP), Imm8(2 * 16));
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#endif
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}
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void JitCompiler::Compile_ADD(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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ADDPS(SRC1, R(SRC2));
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Compile_DestEnable(instr, SRC1);
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}
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void JitCompiler::Compile_DP3(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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if (Common::GetCPUCaps().sse4_1) {
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DPPS(SRC1, R(SRC2), 0x7f);
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} else {
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MULPS(SRC1, R(SRC2));
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC2, R(SRC2), _MM_SHUFFLE(1, 1, 1, 1));
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MOVAPS(SRC3, R(SRC1));
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SHUFPS(SRC3, R(SRC3), _MM_SHUFFLE(2, 2, 2, 2));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 0, 0, 0));
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ADDPS(SRC1, R(SRC2));
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ADDPS(SRC1, R(SRC3));
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}
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Compile_DestEnable(instr, SRC1);
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}
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void JitCompiler::Compile_DP4(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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if (Common::GetCPUCaps().sse4_1) {
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DPPS(SRC1, R(SRC2), 0xff);
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} else {
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MULPS(SRC1, R(SRC2));
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(2, 3, 0, 1)); // XYZW -> ZWXY
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ADDPS(SRC1, R(SRC2));
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 1, 2, 3)); // XYZW -> WZYX
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ADDPS(SRC1, R(SRC2));
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}
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Compile_DestEnable(instr, SRC1);
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}
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void JitCompiler::Compile_DPH(Instruction instr) {
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if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::DPHI) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1i, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2i, SRC2);
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} else {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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}
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if (Common::GetCPUCaps().sse4_1) {
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// Set 4th component to 1.0
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BLENDPS(SRC1, R(ONE), 0x8); // 0b1000
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DPPS(SRC1, R(SRC2), 0xff);
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} else {
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// Reverse to set the 4th component to 1.0
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 1, 2, 3));
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MOVSS(SRC1, R(ONE));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 1, 2, 3));
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MULPS(SRC1, R(SRC2));
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(2, 3, 0, 1)); // XYZW -> ZWXY
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ADDPS(SRC1, R(SRC2));
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MOVAPS(SRC2, R(SRC1));
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SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 1, 2, 3)); // XYZW -> WZYX
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ADDPS(SRC1, R(SRC2));
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}
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Compile_DestEnable(instr, SRC1);
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}
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void JitCompiler::Compile_EX2(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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MOVSS(XMM0, R(SRC1));
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// The following will actually break the stack alignment
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ABI_PushAllCallerSavedRegsAndAdjustStack();
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Compile_PushCallerSavedXMM();
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ABI_CallFunction(reinterpret_cast<const void*>(exp2f));
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Compile_PopCallerSavedXMM();
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ABI_PopAllCallerSavedRegsAndAdjustStack();
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SHUFPS(XMM0, R(XMM0), _MM_SHUFFLE(0, 0, 0, 0));
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MOVAPS(SRC1, R(XMM0));
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Compile_DestEnable(instr, SRC1);
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}
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void JitCompiler::Compile_LG2(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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MOVSS(XMM0, R(SRC1));
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// The following will actually break the stack alignment
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ABI_PushAllCallerSavedRegsAndAdjustStack();
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Compile_PushCallerSavedXMM();
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ABI_CallFunction(reinterpret_cast<const void*>(log2f));
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Compile_PopCallerSavedXMM();
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ABI_PopAllCallerSavedRegsAndAdjustStack();
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SHUFPS(XMM0, R(XMM0), _MM_SHUFFLE(0, 0, 0, 0));
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MOVAPS(SRC1, R(XMM0));
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Compile_DestEnable(instr, SRC1);
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}
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void JitCompiler::Compile_MUL(Instruction instr) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
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MULPS(SRC1, R(SRC2));
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Compile_DestEnable(instr, SRC1);
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}
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void JitCompiler::Compile_SGE(Instruction instr) {
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if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::SGEI) {
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Compile_SwizzleSrc(instr, 1, instr.common.src1i, SRC1);
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Compile_SwizzleSrc(instr, 2, instr.common.src2i, SRC2);
|
|
} else {
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
|
|
}
|
|
|
|
CMPPS(SRC1, R(SRC2), CMP_NLT);
|
|
ANDPS(SRC1, R(ONE));
|
|
|
|
Compile_DestEnable(instr, SRC1);
|
|
}
|
|
|
|
void JitCompiler::Compile_SLT(Instruction instr) {
|
|
if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::SLTI) {
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1i, SRC1);
|
|
Compile_SwizzleSrc(instr, 2, instr.common.src2i, SRC2);
|
|
} else {
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
|
|
}
|
|
|
|
CMPPS(SRC1, R(SRC2), CMP_LT);
|
|
ANDPS(SRC1, R(ONE));
|
|
|
|
Compile_DestEnable(instr, SRC1);
|
|
}
|
|
|
|
void JitCompiler::Compile_FLR(Instruction instr) {
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
|
|
if (Common::GetCPUCaps().sse4_1) {
|
|
ROUNDFLOORPS(SRC1, R(SRC1));
|
|
} else {
|
|
CVTPS2DQ(SRC1, R(SRC1));
|
|
CVTDQ2PS(SRC1, R(SRC1));
|
|
}
|
|
|
|
Compile_DestEnable(instr, SRC1);
|
|
}
|
|
|
|
void JitCompiler::Compile_MAX(Instruction instr) {
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
|
|
// SSE semantics match PICA200 ones: In case of NaN, SRC2 is returned.
|
|
MAXPS(SRC1, R(SRC2));
|
|
Compile_DestEnable(instr, SRC1);
|
|
}
|
|
|
|
void JitCompiler::Compile_MIN(Instruction instr) {
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
|
|
// SSE semantics match PICA200 ones: In case of NaN, SRC2 is returned.
|
|
MINPS(SRC1, R(SRC2));
|
|
Compile_DestEnable(instr, SRC1);
|
|
}
|
|
|
|
void JitCompiler::Compile_MOVA(Instruction instr) {
|
|
SwizzlePattern swiz = { g_state.vs.swizzle_data[instr.common.operand_desc_id] };
|
|
|
|
if (!swiz.DestComponentEnabled(0) && !swiz.DestComponentEnabled(1)) {
|
|
return; // NoOp
|
|
}
|
|
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
|
|
// Convert floats to integers (only care about X and Y components)
|
|
CVTPS2DQ(SRC1, R(SRC1));
|
|
|
|
// Get result
|
|
MOVQ_xmm(R(RAX), SRC1);
|
|
|
|
// Handle destination enable
|
|
if (swiz.DestComponentEnabled(0) && swiz.DestComponentEnabled(1)) {
|
|
// Move and sign-extend low 32 bits
|
|
MOVSX(64, 32, ADDROFFS_REG_0, R(RAX));
|
|
|
|
// Move and sign-extend high 32 bits
|
|
SHR(64, R(RAX), Imm8(32));
|
|
MOVSX(64, 32, ADDROFFS_REG_1, R(RAX));
|
|
|
|
// Multiply by 16 to be used as an offset later
|
|
SHL(64, R(ADDROFFS_REG_0), Imm8(4));
|
|
SHL(64, R(ADDROFFS_REG_1), Imm8(4));
|
|
} else {
|
|
if (swiz.DestComponentEnabled(0)) {
|
|
// Move and sign-extend low 32 bits
|
|
MOVSX(64, 32, ADDROFFS_REG_0, R(RAX));
|
|
|
|
// Multiply by 16 to be used as an offset later
|
|
SHL(64, R(ADDROFFS_REG_0), Imm8(4));
|
|
} else if (swiz.DestComponentEnabled(1)) {
|
|
// Move and sign-extend high 32 bits
|
|
SHR(64, R(RAX), Imm8(32));
|
|
MOVSX(64, 32, ADDROFFS_REG_1, R(RAX));
|
|
|
|
// Multiply by 16 to be used as an offset later
|
|
SHL(64, R(ADDROFFS_REG_1), Imm8(4));
|
|
}
|
|
}
|
|
}
|
|
|
|
void JitCompiler::Compile_MOV(Instruction instr) {
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
Compile_DestEnable(instr, SRC1);
|
|
}
|
|
|
|
void JitCompiler::Compile_RCP(Instruction instr) {
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
|
|
// TODO(bunnei): RCPSS is a pretty rough approximation, this might cause problems if Pica
|
|
// performs this operation more accurately. This should be checked on hardware.
|
|
RCPSS(SRC1, R(SRC1));
|
|
SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 0, 0, 0)); // XYWZ -> XXXX
|
|
|
|
Compile_DestEnable(instr, SRC1);
|
|
}
|
|
|
|
void JitCompiler::Compile_RSQ(Instruction instr) {
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
|
|
// TODO(bunnei): RSQRTSS is a pretty rough approximation, this might cause problems if Pica
|
|
// performs this operation more accurately. This should be checked on hardware.
|
|
RSQRTSS(SRC1, R(SRC1));
|
|
SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 0, 0, 0)); // XYWZ -> XXXX
|
|
|
|
Compile_DestEnable(instr, SRC1);
|
|
}
|
|
|
|
void JitCompiler::Compile_NOP(Instruction instr) {
|
|
}
|
|
|
|
void JitCompiler::Compile_END(Instruction instr) {
|
|
ABI_PopAllCalleeSavedRegsAndAdjustStack();
|
|
RET();
|
|
}
|
|
|
|
void JitCompiler::Compile_CALL(Instruction instr) {
|
|
unsigned offset = instr.flow_control.dest_offset;
|
|
while (offset < (instr.flow_control.dest_offset + instr.flow_control.num_instructions)) {
|
|
Compile_NextInstr(&offset);
|
|
}
|
|
}
|
|
|
|
void JitCompiler::Compile_CALLC(Instruction instr) {
|
|
Compile_EvaluateCondition(instr);
|
|
FixupBranch b = J_CC(CC_Z, true);
|
|
Compile_CALL(instr);
|
|
SetJumpTarget(b);
|
|
}
|
|
|
|
void JitCompiler::Compile_CALLU(Instruction instr) {
|
|
Compile_UniformCondition(instr);
|
|
FixupBranch b = J_CC(CC_Z, true);
|
|
Compile_CALL(instr);
|
|
SetJumpTarget(b);
|
|
}
|
|
|
|
void JitCompiler::Compile_CMP(Instruction instr) {
|
|
using Op = Instruction::Common::CompareOpType::Op;
|
|
Op op_x = instr.common.compare_op.x;
|
|
Op op_y = instr.common.compare_op.y;
|
|
|
|
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
|
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
|
|
|
|
// SSE doesn't have greater-than (GT) or greater-equal (GE) comparison operators. You need to
|
|
// emulate them by swapping the lhs and rhs and using LT and LE. NLT and NLE can't be used here
|
|
// because they don't match when used with NaNs.
|
|
static const u8 cmp[] = { CMP_EQ, CMP_NEQ, CMP_LT, CMP_LE, CMP_LT, CMP_LE };
|
|
|
|
bool invert_op_x = (op_x == Op::GreaterThan || op_x == Op::GreaterEqual);
|
|
Gen::X64Reg lhs_x = invert_op_x ? SRC2 : SRC1;
|
|
Gen::X64Reg rhs_x = invert_op_x ? SRC1 : SRC2;
|
|
|
|
if (op_x == op_y) {
|
|
// Compare X-component and Y-component together
|
|
CMPPS(lhs_x, R(rhs_x), cmp[op_x]);
|
|
MOVQ_xmm(R(COND0), lhs_x);
|
|
|
|
MOV(64, R(COND1), R(COND0));
|
|
} else {
|
|
bool invert_op_y = (op_y == Op::GreaterThan || op_y == Op::GreaterEqual);
|
|
Gen::X64Reg lhs_y = invert_op_y ? SRC2 : SRC1;
|
|
Gen::X64Reg rhs_y = invert_op_y ? SRC1 : SRC2;
|
|
|
|
// Compare X-component
|
|
MOVAPS(SCRATCH, R(lhs_x));
|
|
CMPSS(SCRATCH, R(rhs_x), cmp[op_x]);
|
|
|
|
// Compare Y-component
|
|
CMPPS(lhs_y, R(rhs_y), cmp[op_y]);
|
|
|
|
MOVQ_xmm(R(COND0), SCRATCH);
|
|
MOVQ_xmm(R(COND1), lhs_y);
|
|
}
|
|
|
|
SHR(32, R(COND0), Imm8(31));
|
|
SHR(64, R(COND1), Imm8(63));
|
|
}
|
|
|
|
void JitCompiler::Compile_MAD(Instruction instr) {
|
|
Compile_SwizzleSrc(instr, 1, instr.mad.src1, SRC1);
|
|
|
|
if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI) {
|
|
Compile_SwizzleSrc(instr, 2, instr.mad.src2i, SRC2);
|
|
Compile_SwizzleSrc(instr, 3, instr.mad.src3i, SRC3);
|
|
} else {
|
|
Compile_SwizzleSrc(instr, 2, instr.mad.src2, SRC2);
|
|
Compile_SwizzleSrc(instr, 3, instr.mad.src3, SRC3);
|
|
}
|
|
|
|
if (Common::GetCPUCaps().fma) {
|
|
VFMADD213PS(SRC1, SRC2, R(SRC3));
|
|
} else {
|
|
MULPS(SRC1, R(SRC2));
|
|
ADDPS(SRC1, R(SRC3));
|
|
}
|
|
|
|
Compile_DestEnable(instr, SRC1);
|
|
}
|
|
|
|
void JitCompiler::Compile_IF(Instruction instr) {
|
|
ASSERT_MSG(instr.flow_control.dest_offset > *offset_ptr, "Backwards if-statements not supported");
|
|
|
|
// Evaluate the "IF" condition
|
|
if (instr.opcode.Value() == OpCode::Id::IFU) {
|
|
Compile_UniformCondition(instr);
|
|
} else if (instr.opcode.Value() == OpCode::Id::IFC) {
|
|
Compile_EvaluateCondition(instr);
|
|
}
|
|
FixupBranch b = J_CC(CC_Z, true);
|
|
|
|
// Compile the code that corresponds to the condition evaluating as true
|
|
Compile_Block(instr.flow_control.dest_offset - 1);
|
|
|
|
// If there isn't an "ELSE" condition, we are done here
|
|
if (instr.flow_control.num_instructions == 0) {
|
|
SetJumpTarget(b);
|
|
return;
|
|
}
|
|
|
|
FixupBranch b2 = J(true);
|
|
|
|
SetJumpTarget(b);
|
|
|
|
// This code corresponds to the "ELSE" condition
|
|
// Comple the code that corresponds to the condition evaluating as false
|
|
Compile_Block(instr.flow_control.dest_offset + instr.flow_control.num_instructions - 1);
|
|
|
|
SetJumpTarget(b2);
|
|
}
|
|
|
|
void JitCompiler::Compile_LOOP(Instruction instr) {
|
|
ASSERT_MSG(instr.flow_control.dest_offset > *offset_ptr, "Backwards loops not supported");
|
|
ASSERT_MSG(!looping, "Nested loops not supported");
|
|
|
|
looping = true;
|
|
|
|
int offset = offsetof(decltype(g_state.vs.uniforms), i) + (instr.flow_control.int_uniform_id * sizeof(Math::Vec4<u8>));
|
|
MOV(32, R(LOOPCOUNT), MDisp(UNIFORMS, offset));
|
|
MOV(32, R(LOOPCOUNT_REG), R(LOOPCOUNT));
|
|
SHR(32, R(LOOPCOUNT_REG), Imm8(8));
|
|
AND(32, R(LOOPCOUNT_REG), Imm32(0xff)); // Y-component is the start
|
|
MOV(32, R(LOOPINC), R(LOOPCOUNT));
|
|
SHR(32, R(LOOPINC), Imm8(16));
|
|
MOVZX(32, 8, LOOPINC, R(LOOPINC)); // Z-component is the incrementer
|
|
MOVZX(32, 8, LOOPCOUNT, R(LOOPCOUNT)); // X-component is iteration count
|
|
ADD(32, R(LOOPCOUNT), Imm8(1)); // Iteration count is X-component + 1
|
|
|
|
auto loop_start = GetCodePtr();
|
|
|
|
Compile_Block(instr.flow_control.dest_offset);
|
|
|
|
ADD(32, R(LOOPCOUNT_REG), R(LOOPINC)); // Increment LOOPCOUNT_REG by Z-component
|
|
SUB(32, R(LOOPCOUNT), Imm8(1)); // Increment loop count by 1
|
|
J_CC(CC_NZ, loop_start); // Loop if not equal
|
|
|
|
looping = false;
|
|
}
|
|
|
|
void JitCompiler::Compile_JMP(Instruction instr) {
|
|
ASSERT_MSG(instr.flow_control.dest_offset > *offset_ptr, "Backwards jumps not supported");
|
|
|
|
if (instr.opcode.Value() == OpCode::Id::JMPC)
|
|
Compile_EvaluateCondition(instr);
|
|
else if (instr.opcode.Value() == OpCode::Id::JMPU)
|
|
Compile_UniformCondition(instr);
|
|
else
|
|
UNREACHABLE();
|
|
|
|
FixupBranch b = J_CC(CC_NZ, true);
|
|
|
|
Compile_Block(instr.flow_control.dest_offset);
|
|
|
|
SetJumpTarget(b);
|
|
}
|
|
|
|
void JitCompiler::Compile_Block(unsigned stop) {
|
|
// Save current offset pointer
|
|
unsigned* prev_offset_ptr = offset_ptr;
|
|
unsigned offset = *prev_offset_ptr;
|
|
|
|
while (offset <= stop)
|
|
Compile_NextInstr(&offset);
|
|
|
|
// Restore current offset pointer
|
|
offset_ptr = prev_offset_ptr;
|
|
*offset_ptr = offset;
|
|
}
|
|
|
|
void JitCompiler::Compile_NextInstr(unsigned* offset) {
|
|
offset_ptr = offset;
|
|
|
|
Instruction instr = *(Instruction*)&g_state.vs.program_code[(*offset_ptr)++];
|
|
OpCode::Id opcode = instr.opcode.Value();
|
|
auto instr_func = instr_table[static_cast<unsigned>(opcode)];
|
|
|
|
if (instr_func) {
|
|
// JIT the instruction!
|
|
((*this).*instr_func)(instr);
|
|
} else {
|
|
// Unhandled instruction
|
|
LOG_CRITICAL(HW_GPU, "Unhandled instruction: 0x%02x (0x%08x)", instr.opcode.Value(), instr.hex);
|
|
}
|
|
}
|
|
|
|
CompiledShader* JitCompiler::Compile() {
|
|
const u8* start = GetCodePtr();
|
|
const auto& code = g_state.vs.program_code;
|
|
unsigned offset = g_state.regs.vs.main_offset;
|
|
|
|
ABI_PushAllCalleeSavedRegsAndAdjustStack();
|
|
|
|
MOV(PTRBITS, R(REGISTERS), R(ABI_PARAM1));
|
|
MOV(PTRBITS, R(UNIFORMS), ImmPtr(&g_state.vs.uniforms));
|
|
|
|
// Zero address/loop registers
|
|
XOR(64, R(ADDROFFS_REG_0), R(ADDROFFS_REG_0));
|
|
XOR(64, R(ADDROFFS_REG_1), R(ADDROFFS_REG_1));
|
|
XOR(64, R(LOOPCOUNT_REG), R(LOOPCOUNT_REG));
|
|
|
|
// Used to set a register to one
|
|
static const __m128 one = { 1.f, 1.f, 1.f, 1.f };
|
|
MOV(PTRBITS, R(RAX), ImmPtr(&one));
|
|
MOVAPS(ONE, MDisp(RAX, 0));
|
|
|
|
// Used to negate registers
|
|
static const __m128 neg = { -0.f, -0.f, -0.f, -0.f };
|
|
MOV(PTRBITS, R(RAX), ImmPtr(&neg));
|
|
MOVAPS(NEGBIT, MDisp(RAX, 0));
|
|
|
|
looping = false;
|
|
|
|
while (offset < g_state.vs.program_code.size()) {
|
|
Compile_NextInstr(&offset);
|
|
}
|
|
|
|
return (CompiledShader*)start;
|
|
}
|
|
|
|
JitCompiler::JitCompiler() {
|
|
AllocCodeSpace(1024 * 1024 * 4);
|
|
}
|
|
|
|
void JitCompiler::Clear() {
|
|
ClearCodeSpace();
|
|
}
|
|
|
|
} // namespace Shader
|
|
|
|
} // namespace Pica
|